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BLUENRG-2 数据表(PDF) 94 Page - STMicroelectronics |
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BLUENRG-2 数据表(HTML) 94 Page - STMicroelectronics |
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94 / 190 page  Functional details BlueNRG-2 94/190 DocID030675 Rev 2 Bit Field name Reset RW Description 8 FRX 0x0 RW FRX flushes the receive circuitry (FIFO, fsm).The configuration of the I²C node (register setting) is not affected by the flushing operation. The flushing operation is performed on modules working on different clock domains (system and I²C clocks) and needs several system clock cycles before to be completed. Upon completion, the I²C node (internal logic) clears this bit. The application must not access the Rx FIFO during the flushing operation and should poll on this bit waiting for the completion. 0: Flush operation is completed (I2C controller clears the bit). 1: Flush operation is started and in progress (set by application). 9 DMA_TX_EN 0x0 RW Enables the DMA TX interface. 0: Idle state, the DMA TX interface is disabled. 1: Run state, the DMA TX interface is enabled. On the completion of the DMA transfer, the DMA TX interface is automatically turned off clearing this bit when the end of transfer signal coming from the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same time. 10 DMA_RX_EN 0x0 RW Enables the DMA RX interface. 0: Idle state, the DMA RX interface is disabled. 1: Run state, the DMA RX interface is enabled. On the completion of the DMA transfer, the DMA RX interface is automatically turned off clearing this bit when the end of transfer signal coming from the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same time. 14:12 RESERVED 0x0 R RESERVED 14:13 FON 0x0 RW Filtering on sets the digital filters on the SDA, SCL line, according to the I²C bus requirements, when standard open- drain pads are used: 00b: No digital filters are inserted. 01b: Digital filters (filter 1 ck wide spikes) are inserted. 10b: Digital filters (filter 2 ck wide spikes) are inserted. 11b: Digital filters (filter 4 ck wide spikes) are inserted. 15 FS_1 0x0 RW Force stop enable bit. When set to 1b, the STOP condition is generated. 0: Force stop disabled. 1: Enable force stop. 31:16 RESERVED 0x0 R RESERVED Table 100: I2C - SCR register description: address offset I2CX_BASE_ADDR+0x04 Bit Field name Reset RW Description 6:0 SA7 0x55 RW Slave address 7-bit. SA7 includes the slave address 7-bit or the LSB bits of the slave address 10-bit 9:7 ESA10 0x0 RW Extended slave address 10-bit. ESA10 includes the extension (MSB bits) to the SA7 register field in case of slave addressing mode set to 10-bit |
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