BLUENRG-2 datasheet(39/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

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Table 39: ADC - THRESHOLD_HI register description: address offset ADC_BASE_ADDR+0x24

Bit

Field name

Reset

Description

31:0

THRESHOLD_HI

0xFFFFFFFF

High threshold for window comparator.

Table 40: ADC - THRESHOLD_LO register description: address offset

ADC_BASE_ADDR+0x28

Bit

Field name

Reset

Description

31:0

THRESHOLD_LO

0x00000000

Low threshold for window comparator.

3.7

DMA

3.7.1

Introduction

The BlueNRG-2 device embeds a DMA allowing various combination of data transfer

between the memory and the peripherals without CPU intervention.

Main features are:



Eight independently configurable channels connected to dedicated hardware DMA

requests; software trigger is also supported.



Priorities between requests from channels of the DMA are software programmable

(four levels consisting of very high, high, medium, low). When two channels with same

software priority need attention, channel with lower hardware index will take priority.



Independent source and destination transfer size (byte, half word, word), emulating

packing and unpacking.



Support for circular buffer management.



Event flags (DMA half transfer, DMA transfer complete), logically ORed together in a

single interrupt request for each channel.



Memory-to-memory transfer (RAM only), peripheral-to-memory and memory-to-

peripheral, and peripheral-to-peripheral transfers.



Programmable number of data to be transferred up to 65536 bytes.

3.7.2

Functional overview

The DMA controller performs direct memory transfer by sharing the system bus with the

other masters of the device. The DMA request may stop the CPU access to the system bus

for some bus cycles, when the CPU and DMA are targeting the same destination (memory

or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least

half of the system bus bandwidth (both to memory and peripheral) for the CPU.

3.7.2.1

DMA transactions

After an event, the peripheral sends a request signal to the DMA controller. The DMA

controller serves the request depending on the channel priorities. As soon as the DMA

controller accesses the peripheral, the DMA controller sends an acknowledge to the

peripheral. The peripheral releases its request as soon as it gets the acknowledge from the

DMA controller. Once the request is deasserted by the peripheral, the DMA controller

releases the acknowledge. If there are more requests, the peripheral can initiate the next

transaction.

In summary, each DMA transfer consists of three operations:



The loading of data from the peripheral data register or a location in memory

addressed through an internal current peripheral/memory address register. The start

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