L9679P datasheet(52/272 Pages) STMICROELECTRONICS

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SPI interfaces

L9679P

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DocID029275 Rev 1

SPI interfaces

The L9679P system solution device has many user selectable features controlled through

serial communications by the integrated microcontroller. The device features two SPI

interfaces: one global SPI and one Remote Sensor SPI. The global SPI interface provides

general configuration, control and status functions for the device, while the Remote Sensor

SPI provides dedicated access to Remote Sensor Data and Status Registers.

7.1

SPI protocol

Each SPI interface (Global and Remote Sensor) use their own dedicated set of 4 I/O pins:

CS_G, SCLK_G, MOSI_G and MISO_G for Global SPI; CS_RS, SCLK_RS, MOSI_RS and

MISO_RS for Remote Sensor SPI. Both the SPI interfaces use the same protocol described

here below (the suffix ‘_X’ used in the SPI pin names below is intended to stand for either

‘_G’ or ‘_RS’ depending on the particular SPI interface considered)

The IC SPI interface is composed by an input shift register, an output shift register and four

control signals. MOSI_X is the data input to the input shift register. MISO_X is the data

output from the output shift register. SCLK_X is the clock input used to shift data into the

input shift register or out from the output one while CS_X is the active low chip select input.

All SPI communications are executed in exact 32 bit increments. The general format of the

32 bit transmission for the SPI interface is shown in Table 5.

Data sent to the IC (i.e. MOSI_X) consists of a target read register ID (RID), a target write

data to be written to the target write register indicated by WID. Data returned from the IC

(i.e. MISO_X) consists of a global status word (GSW), read data parity (RPAR) and 20 bits

of data (READ). READ data will be the contents of the target read register as indicated by

the RID bits. The parity bits WPAR and RPAR cover all the 32 bits of the MOSI and MISO

frames, respectively. Odd parity type is used.

The communications is controlled through CS_X, enabling and disabling communication.

When CS_X is at logic high, all SPI communication I/O is tri-stated and no data is accepted.

When CS_X is low, data is latched on the rising edge of SCLK_X and data is shifted on the

falling edge. The MOSI_X pin receives serial data from the master with MSB first. Likewise

for MISO_X, data is read MSB first, LSB last.

The L9679P contains a data validation method through the SCLK_X input to keep

transmissions with not exactly 32 bits from being written to the device. The SCLK_X input

counts the number of received clocks and should the clock counter exceed or count fewer

Table 5.

SPI MOSI and MISO frames layout

SPI register R/W

SPI_MOSI

GID

RID[6:0]

WID[6:0]

WPAR

SPI_MISO

GSW[10:0]

RPAR

READ[19:16]

SPI_MOSI

WRITE[15:0]

SPI_MISO

READ[15:0]

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