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数据搜索系统，热门电子元器件搜索 |
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L9679P 数据表(PDF) 88 Page - STMicroelectronics |
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L9679P 数据表(HTML) 88 Page - STMicroelectronics |
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88 / 272 page  SPI interfaces L9679P 88/272 DocID029275 Rev 1 7.3.14 Watchdog retry configuration register (WD_RETRY_CONF) ID: 28 Type: R/W Read: 2800 Write: 0050 7.3.15 Watchdog timer configuration register (WDTCR) ID: 2A Type: R/W Read: 2A00 Write: 0054 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOSI - WD2_ERR_TH WD2_RETRY_TH X X X X X WD1_RETRY_TH MISO 0 0 0 0 0 0 WD2_ERR_TH WD2_RETRY_TH 0 0 0 0 0 WD1_RETRY_TH WD2_ERR_TH 4 4 - WD2 error counter threshold (number of W2 reset permitted before going to WD2_STOP state) WD2_RETRY_TH 4 4 - WD2 retry counter threshold (number of W2 errors permitted before asserting WD2_Lockout and increment WD2_ERRcnt) WD1_RETRY_TH 7 7 - WD1 retry counter threshold (number of WD errors permitted before latching WD1_LOCKOUT=1) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOSI -X WDTMIN[6:0] WDTDELTA[6:0] MISO 0 000 0 WDTMIN[6:0] WDTDELTA[6:0] WD1_MODE 0 0 - WD1_MODE Updated by WSM RESET or SPI write while in WD1 INIT state 0 Fast WD1 mode - nominal 8 μs timer resolution (2 ms max value) 1 Slow WD1 mode - nominal 64 μs timer resolution (16.3 ms max value) |
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