L9679P datasheet(119/272 Pages) STMICROELECTRONICS

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DocID029275 Rev 1

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L9679P

SPI interfaces

271

7.3.39

PSI5 configuration register for channel x (RSCRx)

PSI5 configuration register for channel 0 (RSCR0)

PSI5 configuration register for channel 1 (RSCR1)

ID:

4A (RSCR0)

4B (RSCR1)

Type:

R/W

Read:

4A00 (RSCR0)

4B00 (RSCR1)

Write:

0094 (RSCR0)

0096 (RSCR1)

MOSI

WSFILT[3:0]

MISO

000

WSFILT[3:0]

PSI5 configured channel

REDUCED_RANGE

0 Tracking speed of base and delta current

0 Fast tracking of Ibase if rx_sat_pre_filt is low; Slow tracking otherwise.

Fast tracking of Idelta if rx_sat_pre_filt is high; Blocked otherwise.

1 Fast tracking of Ibase if current is less than (Ibase+(Idelta/4));

Slow tracking otherwise.

Fast tracking of Idelta if current is higher than (top current -(Idelta/4));

Slow otherwise.

BLOCK_CURR_IN_MSG

0 Tracking enable of base and delta current during message transmission

0 Ibase tracking is enabled during blanking and after start bits recognition.

Idelta tracking is disabled during blanking and enabled after start bits

recognition.

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