L9679P datasheet(155/272 Pages) STMICROELECTRONICS

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L9679P

Deployment drivers

271

Deployment drivers

The squib deployment block consists of 8 independent high side drivers and 8 independent

low side drivers. Squib deployment logic requires a deploy command received through SPI

communications and either an arming condition processed by safing logic or a proper ARMx

input pin assessment, depending on whether the internal safing engine is used or not. Both

conditions must exist in order for the deployment to occur. Once a deployment is initiated, it

can only be terminated by an SSM_RESET event.

L9679P allows all 8 squib loops to be deployed at the very same time or in other possible

timing sequence. Deployment drivers are capable of granting a successful deployment also

in case of short to ground on low-side circuit (SRx pins). Firing voltage capability across high

side circuit is maximum 25 V. High side and low side drivers account for a maximum series

total resistance of 2

. Each loop is granted for a minimum number of deployments of 50,

under all normal operating conditions and with a deployment repetition time higher than 10s.

Both the High and the Low side FET drivers are equipped with passive gate turn-off

circuitries to guarantee the FETs are kept in off state also when the device is unpowered or

during power-up/down transients.

8.1

Control logic

A block diagram representing the deployment driver logic is shown below. Deployment

driver logic features include:



Deploy command logic



Deployment current selection



Deployment current monitoring and deploy success feedback



Diagnostic control and feedback

Figure 27. Deployment driver control blocks

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