L9679P datasheet(197/272 Pages) STMICROELECTRONICS

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L9679P

Safing logic

271

Each safing record has SPI accessible registers defined in the SPI command tables and

summarized below:



Request Mask and Request Target - to understand what sensor the microcontroller is

addressing



Response Mask and Response Target - to identify the sensor response



Data Mask - to extract relevant sensor data from the response.

–

Sensor data is extracted as a bit-wise AND result of the SAF_DATA_MASKx and

monitored RS_MISO data. The configuration of the set bits of the DATAMASK

must be contiguous for both 16-bit and 32-bit records. The 32-bit records are

comprised of Part1 as MSW and Part2 as LSW.

–

The extracted data is then right justified into a 16/32 bit register for 16/32 bit safing

records, respectively, prior to further processing steps which assume data is

signed should be "using two's complement representation".



Safing Threshold - specific value that sets the comparator limit for successful arming



Control:

–

IF, In Frame - to indicate serial data response is ‘in frame’. There are two types of

potential serial data responses, ‘in frame’ and ‘out of frame’.

–

CS - to align safing record with a specific SPI CS. The device contains 5 SPI CS

inputs for the safing function (CS_RS, SAF_CSx)

–

ARM - there are four internal arming signals, each active record is assigned or

mapped to any arming signal. Several safing records can be mapped to a single

arming output. ARMx outputs can be enabled also simultaneously.

–

Dwell - Once an arming condition is detected, the safing record remains armed for

the specified dwell time.

–

Comb (Combined Data) - specific solution for dual axis high-g sensors specifically

oriented off-axis.

–

LimEn (Limit Enable) - to enable PSI5 out-of-range control.

–

LimSel (Limit Select) - to select PSI5 out-of-range thresholds between 8-bit and

10-bit protocol.

–

SPIFLDSEL (SPI Field Select) - to determine which 16-bit field in long SPI

messages (>31 bit) to use for response on MISO of SPI monitor. Don't care for

messages less than 32 bits.

If input packet matches multiple safing records, the safing engine should process all of them

and treat them independently.

Safing record can only be evaluated on the first matching input packet. Any further data

packet matches are ignored (i.e. once CC is set, record can't be processed until CC is

cleared)

The En (Record Enable) bit for any record is programmable as on or off at any time and will

enable/disable the record itself upon the following SATSYNC.

All CC bits are available in one register (SAF_CC) for access in one single SPI read. After

ARMing is achieved and CC is set, no further messages are considered until CC is cleared

via read.

Safing Engine must not process sensor data in any state but Safing state (refer to

Figure 10).

All safing records are cleared on SSM RESET.

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