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CCG2 数据表(PDF) 29 Page - Cypress Semiconductor |
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CCG2 数据表(HTML) 29 Page - Cypress Semiconductor |
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29 / 33 page  EZ-PD™ CCG2 Datasheet Document Number: 001-93912 Rev. *L Page 29 of 33 Acronyms Table 31. Acronyms Used in this Document Acronym Description ADC analog-to-digital converter API application programming interface ARM® advanced RISC machine, a CPU architecture CC configuration channel CCG2 Cable Controller Generation 2 CPU central processing unit CRC cyclic redundancy check, an error-checking protocol CS current sense DFP downstream facing port DIO digital input/output, GPIO with only digital capabil- ities, no analog. See GPIO. DRP dual role port EEPROM electrically erasable programmable read-only memory EMCA a USB cable that includes an IC that reports cable characteristics (e.g., current rating) to the Type-C ports EMI electromagnetic interference ESD electrostatic discharge FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output IC integrated circuit IDE integrated development environment I2C, or IIC Inter-Integrated Circuit, a communications protocol ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO I/O input/output, see also GPIO LVD low-voltage detect LVTTL low-voltage transistor-transistor logic MCU microcontroller unit NC no connect NMI nonmaskable interrupt NVIC nested vectored interrupt controller opamp operational amplifier OCP overcurrent protection OVP overvoltage protection PCB printed circuit board PD power delivery PGA programmable gain amplifier PHY physical layer POR power-on reset PRES precise power-on reset PSoC® Programmable System-on-Chip™ PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RX receive SAR successive approximation register SCL I2C serial clock SDA I2C serial data S/H sample and hold SPI Serial Peripheral Interface, a communications protocol SRAM static random access memory SWD serial wire debug, a test protocol TX transmit Type-C a new standard with a slimmer USB connector and a reversible cable, capable of sourcing up to 100 W of power UART Universal Asynchronous Transmitter Receiver, a communications protocol USB Universal Serial Bus USBIO USB input/output, CCG2 pins used to connect to a USB port XRES external reset I/O pin Table 31. Acronyms Used in this Document (continued) Acronym Description |
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