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CCG2 数据表(PDF) 7 Page - Cypress Semiconductor

部件名 CCG2
功能描述  USB Type-C Port Controller
PDF  33 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CCG2 数据表(HTML) 7 Page - Cypress Semiconductor

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EZ-PD™ CCG2 Datasheet
Document Number: 001-93912 Rev. *L
Page 7 of 33
Pinouts
Group
Name
Pin Map
24-QFN
Ball Location
20-CSP
Pin Map
14-DFN
Description
USB Type-C
Port
CC1
2
B4
3
USB PD connector detect/Configuration Channel 1
CC2
1
A4
N/A
USB PD connector detect/Configuration Channel 2
RD1
3
B3
N/A
Dedicated Rd resistor pin for CC1
Must be left open for cable applications and connected
together with CC1 ball for UFP or DFP with dead battery
applications
GPIOs and
serial interfaces
GPIO
22
C3
N/A
GPIO / SPI_0_CLK / UART_0_ RX
GPIO
18
D3
13
GPIO / SPI_0_MOSI / UART_0_TX
GPIO
13
C2
10
GPIO / I2C_1_SDA / SPI_1_MISO / UART_1_RX
GPIO
10
D2
N/A
GPIO / I2C_1_SCL / SPI_1_CLK / UART_1_TX
GPIO
15
B2
11
GPIO / SPI_1_SEL / UART_1_RTS
GPIO
14
N/A
N/A
GPIO
GPIO
17
N/A
N/A
GPIO
GPIO
21
N/A
N/A
GPIO
GPIO
23
N/A
N/A
GPIO
GPIO
24
N/A
N/A
GPIO
I2C_0_SCL
20
A3
1
GPIO / I2C_0_SCL / SPI_0_MISO / UART_0_RTS
I2C_0_SDA
19
A2
14
GPIO / I2C_0_SDA / SPI_0_SEL / UART_0_CTS
SWD _IO
11
E2
8
SWD IO / GPIO / UART_1_CTS / SPI_1_MOSI
SWD_CLK
12
D1
9
SWD clock / GPIO
RESET
XRES
16
B1
12
Reset input
POWER
VCONN1
5
E4
5
VCONN 1 input (4.0 V to 5.5 V)
VCONN2
4
C4
4
VCONN 2 input (4.0 V to 5.5 V)
VDDIO
8
E1
N/A
1.71-V to 5.5-V supply for I/Os
VCCD
7
A1
6
1.8-V regulator output for filter capacitor
VDDD
9
E3
7
VDDD supply input/output (2.7 V to 5.5 V)
VDDD
6
VDDD supply input/output (2.7 V to 5.5 V)
VSS
EPAD
N/A
EPAD
Ground supply
VSS
D4
2
Ground supply
VSS
C1
Ground supply



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