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EZ-PD™ CCG2 Datasheet

Document Number: 001-93912 Rev. *L

Page 5 of 33

USB-PD Subsystem (SS)

EZ-PD CCG2 has a USB-PD subsystem consisting of a USB

Type-C baseband transceiver and physical-layer logic. This

transceiver performs the BMC and the 4b/5b encoding and

decoding functions as well as the 1.2-V front end. This

subsystem integrates the required termination resistors to

identify the role of the EZ-PD CCG2 solution. RA is used to

identify EZ-PD CCG2 as an accessory or an electronically

marked cable. RD is used to identify EZ-PD CCG2 as a UFP in

a hybrid cable or a dongle. When configured as a DFP, integrated

current sources perform the role of RP or pull-up resistors. These

current sources can be programmed to indicate the complete

range of current capacity on VBUS defined in the Type-C spec.

EZ-PD CCG2 responds to all USB-PD communication. The

EZ-PD CCG2 USB-PD sub-system can be configured to

respond to SOP, SOP', or SOP” messaging.

The USB-PD sub-system contains a 8-bit SAR (Successive

Approximation Register) ADC for analog to digital conversions.

The ADC includes a 8-bit DAC and a comparator. The DAC

output forms the positive input of the comparator. The negative

input of the comparator is from a 4-input multiplexer. The four

inputs of the multiplexer are a pair of global analog multiplex

busses an internal bandgap voltage and an internal voltage

proportional to the absolute temperature. All GPIO inputs can be

connected to the global Analog Multiplex Busses through a

switch at each GPIO that can enable that GPIO to be connected

to the mux bus for ADC use. The CC1, CC2 and RD1 pins are

not available to connect to the mux busses.

Figure 2. USB-PD Subsystem

System Resources

Power System

The power system is described in detail in the section Power on

page 9. It provides assurance that voltage levels are as required

for each respective mode and either delay mode entry (on

power-on reset (POR), for example) until voltage levels are as

required for proper function or generate resets (Brown-Out

Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). EZ-PD

CCG2 can operate from three different power sources over the

range of 2.7 to 5.5 V and has three different power modes,

transitions between which are managed by the power system.

EZ-PD CCG2 provides Sleep and Deep Sleep low-power

modes.

Clock System

The clock system for EZ-PD CCG2 consists of the Internal Main

Oscillator (IMO) and the Internal Low-power Oscillator (ILO).

4b5b

Encoder

SOP

Detect

CRC

4b5b

Decoder

Tx_data

from AHB

Rx_data

to AHB

To/ from AHB

vref

iref

VDDD

To/From system Resources

SOP

Insert

8-bit ADC

From AMUX

CC detect

VConn2 detect

VConn1 detect

CC2

CC1

Ref

8kV IEC ESD

VCONN

Detect

Enable

Logic

8kV IEC ESD

Active

RD1

Comp

Ra Enable

CC control

Enable Logic

TxRx Enable

BMC

Decoder

BMC

Encoder

Digital Baseband PHY

Analog Baseband PHY

VCONN power logic

VCONN2

VCONN1

Deep Sleep

Vref & Iref Gen

vref, iref

SRAM

Deep Sleep Reference Enable

Functional, Wakeup Interrupts

VDDD

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