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EZ-PD™ CCG2 Datasheet

Document Number: 001-93912 Rev. *L

Page 9 of 33

Power

The following power system diagram shows the set of power

supply pins as implemented in EZ-PD CCG2.

EZ-PD CCG2 can operate from three different power sources.

VCONN1 and VCONN2 pins can be used as connections to the

VCONN pins on a Type-C plug of a cable or VCONN-powered

accessory. Each of these inputs support operation over 4.0 to

5.5 V. An internal isolation between VCONN1 and VCONN2 pins

is provided allowing them to be at different levels simultaneously.

CCG2 can be used in EMCA applications with only one or both

VCONN pins as power sources. This is illustrated later in the

section on Applications. Besides being power inputs, each

VCONN pin is also internally connected to a RA termination

resistor required for EMCA and VCONN-powered accessories.

EZ-PD CCG2 can also be operate from 2.7 to 5.5 V when

operated from the VDDD supply pin. VCONN-powered

accessory applications require that CCG2 work down to 2.7 V. In

such applications, both the VDDD and VCONN pins should be

connected to the VCONN pin of the Type-C plug in the

accessory.

In UFP, DFP, and DRP applications, CCG2 can be operated from

VDDD as the only supply input. In such applications, the VCONN

pins are left open. In DFP applications, the lowest VDDD level

that CCG2 can operate is 3.0 V due to the need to support

disconnect detection thresholds of up to 2.7 V.

A separate I/O supply pin, VDDIO, allows the GPIOs to operate

at levels from 1.71 to 5.5 V. The VDDIO pin can be equal to or

less than the voltages connected to the VCONN1, VCONN2, and

VDDD pins. The independent VDDIO supply is not available on

the 14-DFN package. On this package, the VDDIO rail is

internally connected to the VDDD rails.

The VCCD output of EZ-PD CCG2 must be bypassed to ground

via an external capacitor (in the range of 1 to 1.6 µF; X5R

ceramic or better).

Bypass capacitors must be used from VDDD and VCONN pins

to ground; typical practice for systems in this frequency range is

to use a 0.1-µF capacitor. Note that these are simply rules of

thumb and that for critical applications, the PCB layout, lead

inductance, and the bypass capacitor parasitic should be

simulated to design and obtain optimal bypassing.

An example of the power supply bypass capacitors is shown in

Figure 6.

Figure 6. EZ-PD CCG2 Power and Bypass Scheme Example

VSS

VCONN2

VDDD

Core Regulator

(srsslt)

VCONN1

VCCD

Core

VDDIO

GPIO

Tx/Rx

1uF

0.1uF

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