 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
DS3153N 数据表(PDF) 15 Page - Dallas Semiconductor |
|
|
|||||||||||||||||||||||||||||
DS3153N 数据表(HTML) 15 Page - Dallas Semiconductor |
|
|
15 / 60 page  DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs 15 of 60 5. REGISTER DESCRIPTIONS When the DS315x is configured in CPU bus mode (HW = 0), the registers shown in Table 5-A are accessible through the CPU bus interface. All registers for the LIU ports are forced to their default values during an internal power-on reset or when the RST pin is driven low. Setting an LIU’s RST bit high forces all registers for that LIU to their default values. All register bits marked “—” must be written 0 and ignored when read. The TEST registers must be left at their reset value of 00h for normal operation. On the DS3153, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored. Reads from LIU 4 address space return all zeros. On the DS3152, address line A5 is not present, limiting the address space to the LIU 1 and 2 registers. On the DS3151, address lines A5 and A4 are not present, limiting the address space to the LIU 1 registers. Table 5-A. Register Map ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LIU 1 00h GCR1 E3M STS LLB RLB TDSA TDSB — RST 01h TCR1 — TBIN TCINV TJA TPD TTS TLBO — 02h RCR1 ITU RBIN RCINV RJA RPD RTS RMON RCVUD 03h SR1 — — TDM PRBS — — RLOL RLOS 04h SRL1 — — TDML PRBSL PBERL RCVL RLOLL RLOSL 05h SRIE1 — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE 06h RCVL1 RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] 07h RCVH1 RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] 08h–0Fh TEST — — — — — — — — LIU 2 10h GCR2 E3M STS LLB RLB TDSA TDSB -- RST 11h TCR2 — TBIN TCINV TJA TPD TTS TLBO -- 12h RCR2 ITU RBIN RCINV RJA RPD RTS RMON RCVUD 13h SR2 — — TDM PRBS — — RLOL RLOS 14h SRL2 — — TDML PRBSL PBERL RCVL RLOLL RLOSL 15h SRIE2 — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE 16h RCVL2 RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] 17h RCVH2 RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] 18h–1Fh TEST — — — — — — — — LIU 3 20h GCR3 E3M STS LLB RLB TDSA TDSB — RST 21h TCR3 — TBIN TCINV TJA TPD TTS TLBO — 22h RCR3 ITU RBIN RCINV RJA RPD RTS RMON RCVUD 23h SR3 — — TDM PRBS — — RLOL RLOS 24h SRL3 — — TDML PRBSL PBERL RCVL RLOLL RLOSL 25h SRIE3 — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE 26h RCVL3 RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] 27h RCVH3 RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] 28h–2Fh TEST — — — — — — — — LIU 4 30h GCR4 E3M STS LLB RLB TDSA TDSB — RST 31h TCR4 — TBIN TCINV TJA TPD TTS TLBO — 32h RCR4 ITU RBIN RCINV RJA RPD RTS RMON RCVUD 33h SR4 — — TDM PRBS — — RLOL RLOS 34h SRL4 — — TDML PRBSL PBERL RCVL RLOLL RLOSL 35h SRIE4 — — TDMIE PRBSIE PBERIE RCVIE RLOLIE RLOSIE 36h RCVL4 RCV[7] RCV[6] RCV[5] RCV[4] RCV[3] RCV[2] RCV[1] RCV[0] 37h RCVH4 RCV[15] RCV[14] RCV[13] RCV[12] RCV[11] RCV[10] RCV[9] RCV[8] 38h–3Fh TEST — — — — — — — — Note 1: Underlined bits are read-only; all other bits are read-write. Note 2: The registers are named REGn, where n = the LIU number (1, 2, 3, or 4). Note 3: The bit names are the same for each LIU register set. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
