DS3153N datasheet(38/60 Pages) DALLAS

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

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Table 13-C. Framer Interface Timing

(VDD = 3.3V

±5%, TA = -40°C to +85°C.) (Figure 13-1 and Figure 13-2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

(Note 4)

22.4

(Note 5)

29.1

RCLK/TCLK Clock Period

(Note 6)

19.3

RCLK Duty Cycle

t2/t1, t3/t1

(Notes 7, 8)

TCLK Duty Cycle

t2/t1, t3/t1

(Note 8)

MCLK Duty Cycle

t2/t1, t3/t1

(Note 8)

TPOS/TDAT, TNEG to TCLK Setup

Time

(Notes 8, 9)

TPOS/TDAT, TNEG Hold Time

(Notes 8, 9)

RCLK to RPOS/RDAT, RNEG/RLCV,

and PRBS Value Change

(Notes 7, 8, 10)

RCLK Rise and Fall Time

(Notes 8, 11)

TCLK Rise and Fall Time

(Notes 8, 12)

Note 4: DS3 mode.

Note 5: E3 mode.

Note 6: STS-1 mode.

Note 7: Outputs loaded with 25pF, measured at 50% threshold.

Note 8: Not tested during production test.

Note 9: When TCINV = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCINV = 1, TPOS/TDAT and TNEG are

sampled on the falling edge of TCLK.

Note 10: When RCINV = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCINV = 1, RPOS/RDAT and

RNEG/RLCV are updated on the rising edge of RCLK.

Note 11: Outputs loaded with 25pF, measured between VOL (max) and VOH (min).

Note 12: Measured between VIL (max) and VIH (min).

Figure 13-1. Transmitter Framer Interface Timing Diagram

TCLK (INVERTED)

TPOS/TDAT,

TNEG

TCLK (NORMAL)

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