DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

40 of 60

Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes

PARAMETER

MIN

TYP

MAX

UNITS

DS3 Output Pulse Amplitude, TLBO = 0 (Note 17)

700

800

900

mVpk

DS3 Output Pulse Amplitude, TLBO = 1 (Note 17)

520

700

800

mVpk

STS-1 Output Pulse Amplitude, TLBO = 0 (Note 17)

700

800

1100

mVpk

STS-1 Output Pulse Amplitude, TLBO = 1 (Note 17)

520

700

850

mVpk

Ratio of Positive and Negative Pulse-Peak Amplitudes

0.9

1.1

DS3 Unframed All-Ones Power Level at 22.368MHz, 3kHz Bandwidth

-1.8

+5.7

dBm

DS3 Unframed All-Ones Power Level at 44.736MHz vs. Power Level at

22.368MHz, 3kHz Bandwidth

-20

dB

Intrinsic Jitter Generation (Note 18)

0.02

0.05

Table 13-G. Transmitter Output Characteristics—E3 Mode

PARAMETER

MIN

TYP

MAX

UNITS

Output Pulse Amplitude (Note 17)

900

1000

1100

mVpk

Pulse Width

14.55

ns

Ratio of Positive and Negative Pulse Amplitudes (at Centers of Pulses)

0.95

1.05

Ratio of Positive and Negative Pulse Widths (at Nominal Half Amplitude)

0.95

1.05

Intrinsic Jitter Generation (Note 18)

0.02

0.05

Note 17: Measured on the line side (i.e., the BNC connector side) of the 2:1 transmit transformer (Figure 1-1).

Note 18: Measured with jitter-free clock applied to TCLK and a bandpass jitter filter with 10Hz and 800kHz cutoff frequencies. Not tested during

production test.

Table 13-H. CPU Bus Timing

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Setup Time for A[5:0] Valid to

CS Active (Notes 19, 20)

t1

0

ns

Setup Time for

CS Active to RD, WR, or DS Active

t2

0

ns

Delay Time from

RD or DS Active to D[7:0] Valid

t3

65

ns

Hold Time from

RD or WR or DS Inactive to CS Inactive

t4

0

ns

Delay from

CS or RD or DS Inactive to D[7:0] Invalid or Tri-State

(Note 21)

t5

2

20

ns

Wait Time from

WR or DS Active to Latch D[7:0]

t6

65

ns

D[7:0] Setup Time to

WR or DS Inactive

t7

10

ns

D[7:0] Hold Time from

WR or DS Inactive

t8

2

ns

A[5:0] Hold Time from

WR or RD or DS Inactive

t9

5

ns

RD, WR, or DS Inactive Time

t10

75

ns

Muxed Address Valid to ALE Falling (Note 22)

t11

10

ns

Muxed Address Hold Time (Note 22)

t12

10

ns

ALE Pulse Width (Note 22)

t13

30

ns

Setup Time for ALE High or Muxed Address Valid to

CS Active

(Note 22)

t14

0

ns

Note 19: D[7:0] loaded with 50pF when tested as outputs.

Note 20: If a gapped clock is applied on TCLK and diagnostic loopback is enabled, read cycle time must be extended by the length of the

largest TCLK gap.

Note 21: Not tested during production test.

Note 22: In nonmultiplexed bus applications (Figure 13-3), ALE should be wired high. In multiplexed bus applications (Figure 13-4), A[5:0]

should be wired to D[5:0] and the falling edge of ALE latches the address.