Document Number: 002-01122 Rev.*L

Page 38 of 59

S29AS016J

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,

then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the

device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-

suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 36).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is

written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.

Table on page 40 shows the outputs for Toggle Bit I on DQ6. Figure 12.2 on page 39 shows the toggle bit algorithm in flowchart

form, and Reading Toggle Bits DQ6/DQ2 on page 38 explains the algorithm. Figure 18.8 on page 49 shows the toggle bit timing

diagrams. Figure 18.9 on page 49 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2:

Toggle Bit II on page 38.

12.4

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded

Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#

pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use

either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-

suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table

on page 40 to compare outputs for DQ2 and DQ6.

Figure 12.2 on page 39 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 38

explains the algorithm. See also the DQ6: Toggle Bit I on page 37 subsection. Figure 18.8 on page 49 shows the toggle bit timing

diagram. Figure 18.9 on page 49 shows the differences between DQ2 and DQ6 in graphical form.

12.5

Reading Toggle Bits DQ6/DQ2

Refer to Figure 12.2 on page 39 for the following discussion. Whenever the system initially begins reading toggle bit status, it must

read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the

value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data (at

DQ7–DQ0 in byte mode or DQ15–DQ0 in word mode) on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note

whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has

successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully,

and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system

may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous

paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the operation (top of Figure 12.2 on page 39).