Document Number: 002-01122 Rev.*L

Page 49 of 59

S29AS016J

Figure 18.7 Data# Polling Timings (During Embedded Algorithms)

Note

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 18.8 Toggle Bit Timings (During Embedded Algorithms)

Note

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 18.9 DQ2 vs. DQ6 for Erase and Erase Suspend Operations

Note

The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

WE#

CE#

OE#

High Z

High Z

DQ7

DQ0–DQ6

RY/BY#

Complement

True

Addresses

VA

VA

VA

Status Data

Complement

Status Data

True

Valid Data

Valid Data

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

Addresses

VA

VA

VA

Valid Data

Valid Status

Valid Status

(first read)

(second read)

(stops toggling)

Valid Status

VA

Enter

Erase

Erase

Erase

Enter Erase

Suspend Program

Erase Suspend

Read

Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Suspend

Program

Resume

Embedded

Erasing