HCV1707R1-R48-R datasheet(37/41 Pages) VICOR

37 / 41 page

Cool-Power® ZVS Switching Regulators

Rev 1.5

Page 37 of 41

03/2018

PI352x-00

Layout Guidelines

To optimize maximum efficiency and low noise performance

from a PI352x-00 design, layout considerations are necessary.

Reducing trace resistance and minimizing high current loop

returns along with proper component placement will contribute

to optimized performance.

A typical buck converter circuit is shown in Figure 97. The

potential areas of high parasitic inductance and resistance are the

circuit return paths, shown as LR below.

The path between the COUT and CIN capacitors is of particular

importance since the AC currents are flowing through both of

them when Q1 is turned on. Figure 98, schematically, shows the

reduced trace length between input and output capacitors. The

shorter path lessens the effects that copper trace parasitics can

have on the PI352x-00 performance.

When Q1 is on and Q2 is off, the majority of CIN’s current is used

to satisfy the output load and to recharge the COUT capacitors.

When Q1 is off and Q2 is on, the load current is supplied by the

inductor and the COUT capacitor as shown in Figure 99. During

this period CIN is also being recharged by the VIN. Minimizing CIN

loop inductance is important to reduce peak voltage excursions

when Q1 turns off. Also, the difference in area between the CIN

loop and COUT loop is vital to minimize switching and GND noise.

Figure 100 illustrates the tight path between CIN and COUT

(and VIN and VOUT) for the high AC return current. The

PI352x-00 evaluation board uses a layout optimized for

performance in this way.

OUT

Figure 97 — Typical Buck Regulator

OUT

Figure 98 — Current flow: Q1 closed

OUT

Figure 99 — Current flow: Q2 closed

PGND

VOUT

VS1

VIN

Inductor

ZVS-

Buck

SIP

Figure 100 — Recommended layout for Optimized AC Current

within the SiP, Inductor, and Ceramic Input and

Output Capacitors

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