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数据搜索系统，热门电子元器件搜索 |
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HCV1707R1-R48-R 数据表(PDF) 5 Page - Vicor Corporation |
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HCV1707R1-R48-R 数据表(HTML) 5 Page - Vicor Corporation |
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5 / 41 page  Cool-Power® ZVS Switching Regulators Rev 1.5 Page 5 of 41 03/2018 PI352x-00 Pin Description Name Location I/O Description VS1 Block 1 Power Switching Node: and ZVS sense for power switches. VIN Block 3 Power Input Voltage: and sense for UVLO, OVLO and feed forward ramp. VDR 5K I/O Gate Driver VCC: Internally generated 5.1V. May be used as a bias supply for low power external loads. See Application Description for important considerations. SYNCI 4K I Synchronization Input: Synchronize to the falling edge of external clock frequency. SYNCI is a high impedance digital input node and should always be connected to SGND when not in use. The PI352x-00 family is not optimized for external synchronization functionality. Refer to Application Description of Parallel Operation for details. SYNCO 3K O Synchronization Output: Outputs a high signal at the start of each clock cycle for the longer of ½ of the minimum period or the on time of the high side power MOSFET. TEST1 2K I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. TEST2 1K I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. TEST3 1J I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. TEST4 1H I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. TEST5 1E I/O Test Connections: Use only with factory guidance. Connect to SGND for proper operation. PWRGD 1G O Power Good: High impedance when regulator is operating and VOUT is in regulation. Otherwise pulls to SGND. EN 1F I/O Enable Input: Regulator enable control. When asserted active or left floating: regulator is enabled. Otherwise regulator is disabled. SGND Block 5 Signal Ground: Internal logic ground for EA, TRK, SYNCI, SYNCO communication returns. SGND and PGND are star connected within the regulator package. TRK 1C I Soft-Start and Track Input: An external capacitor may be connected between TRK pin and SGND to increase the rise time of the internal reference during soft start. COMP 1B O Compensation Capacitor: Connect capacitor for control loop dominant pole. See Error Amplifier section for details. A default CCOMP of 4.7nF is used in the example. EAO 1A O Error amp output: External connection for additional compensation and current sharing. EAIN 2A I Error Amp Inverting Input: Connection for the main VOUT feedback divider tap. VDIFF 3A O Independent Amplifier Output: Active only when module is enabled. VSN 4A I Independent Amplifier Inverting Input: If unused connect in unity gain. VSP 5A I Independent Amplifier Non-Inverting Input: If unused connect to SGND. VOUT 6A,B Power Direct VOUT Connect: for per-cycle internal clamp node and feed-forward ramp. PGND Block2 Power Power Ground: VIN and VOUT power returns. |
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