AD8364ACPZ-R2 datasheet(35/44 Pages) AD

35 / 44 page

Data Sheet

AD8364

Rev. C | Page 35 of 44

ALTERING THE SLOPE

None of the changes to operating conditions discussed so far

affect the logarithmic slope, VSLOPE, in Equation 7. The slope can

readily be altered by controlling the fraction of OUT[A, B] that

is fed back to the setpoint interface at the VST[A, B] pin. When

the full signal from OUT[A, B] is applied to VST[A, B], the slope

assumes the nominal value of 50 mV/dB. It can be increased by

including a voltage divider between these pins, as shown in

Figure 76. Moderately low resistance values must be used to

minimize scaling errors due to the approximately 70 kΩ input

resistance at the VST[A, B] pin. Keep in mind that this resistor

string also loads the output, and it eventually reduces the load-

driving capabilities if very low values are used. Equation 17 can

be used to calculate the resistor values.

R1 = R2' (SD/50 − 1)

(17)

where:

SD is the desired slope, expressed in mV/dB.

R2' is the value of R2 in parallel with 70 kΩ.

For example, using R1 = 1.65 kΩ and R2 = 1.69 kΩ (R2' =

1.649 kΩ), the nominal slope is increased to 100 mV/dB. This

choice of scaling is useful when the output is applied to a digital

voltmeter because the displayed number directly reads as a

decibel quantity with only a decimal point shift.

Operating at a high slope is useful when it is desired to measure

a particular section of the input range in greater detail. A

measurement range of 60 dB corresponds to a 6 V change in

VOUT at this slope, exceeding the capacity of the AD8364

output stage when operating on a 5 V supply. This requires that

the intercept is repositioned to place the desired input range

section within a window corresponding to an output range of

0.1 V ≤ VOUT ≤ 4.8 V, a 47 dB range.

Using the arrangement shown in Figure 77, an output of 0.4 V

corresponds to the lower end of the desired range, and an output of

3.5 V corresponds to the upper limit with 3 dB of margin at each

end of the range, nominally −32 dBm to −1 dBm with the

intercept at −35.6 dBm. Note that R2 is connected to VREF

rather than ground. R3 is needed to ensure that the AD8364

reference buffer is correctly loaded.

When the slope is raised by some factor, the loop capacitor,

CLP[A, B], must be raised by the same factor to ensure stability

and to preserve a chosen averaging time. The slope can be

lowered by placing a voltage divider after the output pin,

following standard practice.

VOUT

CHANNEL A

TruPwr™

CHANNEL B

TruPwr™

VPSA

VPSB

INHB

INLB

COMR

PWDN

INLA

INHA

VSTA

VSTB

OUTB

FBKB

OUTN

OUTP

FBKA

OUTA

BIAS

TEMP

OUTA

OUTB

ISIG2

ITGT2

VGA

CONTROL

VGA

CONTROL

ISIG2

ITGT2

Figure 76. External Network to Raise Slope

4.02k



4.32k



VOUT

CHANNEL A

TruPwr™

CHANNEL B

TruPwr™

VPSA

VPSB

INHB

INLB

COMR

PWDN

INLA

INHA

VSTA

VSTB

OUTB

FBKB

OUTN

OUTP

FBKA

OUTA

BIAS

TEMP

OUTA

OUTB

ISIG2

ITGT2

VGA

CONTROL

VGA

CONTROL

ISIG2

ITGT2

Figure 77. Scheme Providing 100 mV/dB Slope for Operation over a 3 mV to

300 mV Input Range

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