AD8364ACPZ-R2 datasheet(18/44 Pages) AD

18 / 44 page

AD8364

Data Sheet

Rev. C | Page 18 of 44

THEORY OF OPERATION

The AD8364 is a dual-channel, 2.7 GHz, true rms responding

detector with 60 dB measurement range. It incorporates two

AD8362 channels with shared reference circuitry (See the AD8362

datasheet for more information). Multiple enhancements have been

made to the AD8362 cores to improve measurement accuracy.

Log-conformance peak-to-peak ripple has been reduced to <±0.2

dB over the entire dynamic range. Temperature stability of the

rms output measurements provides <±0.5 dB error over the

specified temperature range of −40°C to 85°C through proprietary

techniques. The use of well-matched channels offers extremely

temperature-stable difference outputs, OUTP and OUTN.

Given well-matched channels through IC integration, the rms

measurement outputs, OUTA and OUTB, drift in the same

manner. With OUTP shorted to FBKA, the function at OUTP is

OUTP = OUTA – OUTB + VLVL

(1)

When OUTN is shorted to FBKB, the function at OUTN is

OUTN = OUTB – OUTA + VLVL

(2)

OUTP and OUTN are insensitive to the common drift due to

the difference cancellation of OUTA and OUTB.

The AD8364 is a fully calibrated rms-to-dc converter capable of

operating on signals of a few hertz to 2.7 GHz or more. Unlike

logarithmic amplifiers, the AD8364 response is waveform

independent. The device accurately measures waveforms that

have a high peak-to-rms ratio (crest factor). Figure 50 shows a

block diagram.

A single channel of the AD8364 consists of a high performance

AGC loop. As shown in Figure 51, the AGC loop comprises

a wide bandwidth variable gain amplifier (VGA), square law

detectors, an amplitude target circuit, and an output driver. For

a more detailed description of the functional blocks, see the

AD8362 data sheet.

CHANNEL A

TruPwr™

CHANNEL B

TruPwr™

VPSA

VPSB

INHB

INLB

COMR

PWDN

INLA

INHA

VSTA

VSTB

OUTB

FBKB

OUTN

OUTP

FBKA

OUTA

BIAS

TEMP

OUTA

OUTB

ISIG2

ITGT2

VGA

CONTROL

VGA

CONTROL

ISIG2

ITGT2

Figure 50. Block Diagram

VIN

VREF × 0.03

VSIG

VST[A, B]

CLP [A, B]

VREF

2.5V

OFFSET

NULLING

INH[A, B]

INL[A, B]

VGA

SETPOINT

INTERFACE

OUTPUT

BUFFER

CHP[A, B]

VST[A, B]

VREF

GSET

BAND GAP

REFERENCE

TEMPERATURE

COMPENSATION

CLPF

EXTERNAL

ADJ[A, B]

OUT[A, B]

ACOM

Figure 51. Single-Channel Details

AD8364ACPZ-R2 数据表(PDF) 18 Page - Analog Devices

AD8364ACPZ-R2 数据表(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载