AD8364ACPZ-R2 datasheet(36/44 Pages) AD

36 / 44 page

AD8364

Data Sheet

Rev. C | Page 36 of 44

CHOOSING THE RIGHT VALUE

FOR CHP[A, B] AND CLP[A, B]

The AD8364 VGA includes an offset cancellation loop, which

introduces a high-pass filter effect in the transfer function. The

corner frequency, fHP, of this filter must be below that of the lowest

input signal in the desired measurement bandwidth frequency

to properly measure the amplitude of the input signal. The

required value of the external capacitor is given by

CHP[A, B] = 200 μF/(2 × π × fHP )(fHP in Hz)

(18)

Thus, for operation at frequencies down to 100 kHz, CHP[A, B]

must be 318 pF.

In the standard connections for the measurement mode, the

VST[A, B] pin is tied to OUT[A, B]. For small changes in input

amplitude (a few decibels), the time-domain response of this

loop is essentially linear with a 3 dB low-pass corner frequency

of nominally fLP = 1/(2 × π × CLP[A, B] × 1.1 kΩ). Internal time

delays around this local loop set the minimum recommended

value of this capacitor to about 300 pF, making fLP = 482 kHz.

For operation at lower signal frequencies, or whenever the

averaging time needs to be longer, use

CLP[A, B] = 900 μF/2 × π × fLP (fLP in Hz)

(19)

When the input signal exhibits large crest factors, such as a

WCDMA signal, CLP[A, B] must be much larger than might at

first seem necessary. This is due to the presence of significant low

frequency components in the complex, pseudo random modu-

lation, which generates fluctuations in the output of the AD8364.

RF BURST RESPONSE TIME

RF burst response time is important for modulated signals that

have large steps in power, such as a single carrier EVDO that

has the potential for a greater than 20 dB burst of power (for

approximately 200 μs out of every 800 μs).

Accurate power detection for signals with RF bursts is achieved

when the AD8364 is able to respond quickly to the change in RF

power; however, the response time is limited by the capacitors

placed on Pins CLP[A, B], CHP[A, B], and DEC[A, B].

Capacitors placed on the DEC[A, B] pins affect the response time

the least and must be chosen as stated in the RF Input Interface

section. Capacitors placed on CHP[A, B] and CLP[A, B] must be

chosen according to the equations in the Choosing the Right

Value for CHP[A, B] and CLP[A, B] section and the response time

for the AD8364 must be evaluated. If the response time is not

fast enough to follow the burst response, the values for CLP[A, B]

must be decreased. The capacitor values placed on the CLP[A, B]

have the largest effect on the rise and fall times. The capacitor

values placed on CHP[A, B] affect the rising and falling corner

of the response (overshoot or under-shoot); however, the falling

corner is most likely swamped out by the effect of CLP[A, B].

Once the response time is set so that the AD8364 is just able to

follow the RF burst requirements (within the tolerance of the

capacitors), the output of the AD8364 must be evaluated with

an oscilloscope. If there is ripple on the output (due to the

modulated signal), averaging may need to be performed on

the DSP to achieve a true rms response. Figure 44 and Figure 45

may help in determining the proper CLP[A, B] values to use.

SINGLE-ENDED INPUT OPERATION

For optimum operation, the RF inputs to the AD8364 must be

driven differentially. However, the AD8364 RF inputs can also

be driven in a single-ended configuration with reduced dynamic

range. Figure 78 shows a recommended input configuration for

a single channel.

Figure 79 shows the performance obtained with the configuration

shown in Figure 78. The user must note that the dynamic range

performance suffers in single-ended configuration due to the

inherent amplitude and phase imbalance at the RF inputs.

However, at low frequency the dynamic range is quite good and

users trying to detect low frequency or baseband signals may

want to consider this as an option. At frequencies greater than

450 MHz, the dynamic range decreases to about 20 dB, reducing

the AD8364 usefulness for many applications. Performance in

single-ended configuration is subject to circuit board layout

(see the Printed Circuit Board Considerations section).

100



100



INHx

INLx

Figure 78. Recommended Input Configuration for Single-Ended Input Drive

RF INPUT (dBm)

–60

–40

–30

–50

–20

–10

5.0

4.0

3.0

2.0

4.5

3.5

2.5

1.5

1.0

0.5

50MHz

100MHz

45 MHz

50MHz Error

100MHz ERROR

450MHz ERROR

Figure 79. Single-Ended Performance for

the Configuration Shown in Figure 78

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