AD8364ACPZ-R2 datasheet(19/44 Pages) AD

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Data Sheet

AD8364

Rev. C | Page 19 of 44

SQUARE LAW DETECTOR AND AMPLITUDE

TARGET

The output of the VGA, called VSIG, is applied to a wideband

square law detector. The detector provides the true rms

response of the RF input signal, independent of waveform, up

to a crest factor of 6. The detector output, called ISQU, is a

fluctuating current with positive mean value. The difference

between ISQU and an internally generated current, ITGT[A,B], is

integrated by CF and a capacitor attached to CLP[A, B]. CF is

the on-chip 25 pF filter capacitor. CLP[A, B] can be used to

arbitrarily increase the averaging time while trading off

response time. When the AGC loop is at equilibrium,

MEAN(ISQU) = ITGT[A, B]

(3)

This equilibrium occurs only when

MEAN(VSIG2) = VTGT[A, B]2

(4)

where VTGT is an attenuated version of the VREF voltage.

Because the square law detectors are electrically identical and

well matched, process and temperature dependent variations

are effectively cancelled.

By forcing the above identity through varying the VGA

setpoint, it is apparent that

RMS(VSIG) = √(MEAN(VSIG2)) = √(VTGT2) = VTGT

(5)

Substituting the value of VSIG, we have

RMS(G0 × RFIN exp(−VST[A, B]/VGNS)) = VTGT

(6)

When connected as a measurement device VST[A, B] =

OUT[A, B]. Solving for OUT[A, B] as a function of RFIN,

OUT[A, B] = VSLOPE × Log10(RMS(RFIN)/VZ)

(7)

where VSLOPE is laser trimmed to 1 V/decade (or 50 mV/dB) at

100 MHz. VZ is the intercept voltage, since Log 10(1) = 0 when

RMS(RFIN) = VZ. If desired, the effective value of VSLOPE may be

altered by using a resistor divider from OUT[A, B] to drive

VST[A, B]. The intercept, VZ, is also laser trimmed to 180 µV

(−62 dBm, referred to 50 Ω) with a CW signal at 100 MHz. This

value is extrapolated, because OUT[A, B] do not respond to input

of less than approximately −55 dBm with differential drive.

In most applications, the AGC loop is closed through the

setpoint interface, VST[A, B]. In measurement mode, OUT[A, B]

are tied to VST[A, B], respectively. In controller mode, a control

voltage is applied to VST[A, B]. Pins OUT[A, B] drive the control

input of a system. The RF feedback signal to the input pins is

forced to have an rms value determined by VSTA or VSTB.

RF INPUT INTERFACE

The AD8364 RF inputs are connected as shown in Figure 52.

There are 100 Ω resistors connected between DEC[A, B] and

INH[A, B] and also between DEC[A, B] and INL[A, B]. The

DEC[A, B] pins have a dc level established as (7 × VPS[A, B] +

55 × VBE)/30. With a 5 V supply, DEC[A, B] is approximately

2.5 V.

Signal-coupling capacitors must be connected from the input

signal to the INH[A, B] and INL[A, B] pins. The high-pass

corner is

fhigh-pass = 1/(2 × π × 100 × C)

(8)

A decoupling capacitor must be connected from DEC[A, B] to

ground to attenuate any signal at the midpoint. A 100 pF and

0.1 µF cap from DEC[A, B] to ground are recommended, with a

1 nF coupling capacitor such that signals greater than 1.6 MHz

can be measured. For coupling signals less than 1.6 MHz,

100 × Ccoupling for the DEC[A, B] capacitor generally can be used.

VGA

COM[A, B]

VSP[A, B]

VIN

COM[A, B]

VSP[A, B]

COM[A, B]

VSP[A, B]

DEC[A, B]

INH[A, B]

INL[A, B]

100

Ω

100

Ω

Figure 52. AD8364 RF Inputs

OFFSET COMPENSATION

An offset-nulling loop is used to address small dc offsets in the

VGA. The high-pass corner frequency of this loop is internally

preset to about 1 MHz using an on-chip capacitor of 25 pF

(1/(2 × 5K × 25 pF)), which is sufficiently low for most HF

applications. The high-pass corner can be reduced by a

capacitor from CHP[A, B] to ground. The input offset voltage

varies depending on the actual gain at which the VGA is

operating and, thus, on the input signal amplitude. When an

excessively large value of CHP[A, B] is used, the offset

correction process may lag the more rapid changes in the VGA

gain, which may increase the time required for the loop to fully

settle for a given steady input amplitude.

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