AD9577BCPZ-R7 datasheet(30/44 Pages) AD

30 / 44 page

AD9577

Data Sheet

Rev. A | Page 30 of 44

OUTPUT CHANNEL DIVIDERS

Between each VCO and its associated chip outputs, there are

two divider stages: a VCO divider that has a divide ratio between

2 and 6 and an output divider that can be set to divide between

1 and 32. This cascade of dividers allows a minimum output

channel divide ratio of 2 and a maximum of 192. With VCO

frequencies ranging between 2.15 GHz and 2.55 GHz, the part

can be programmed to spot frequencies over a continuous

frequency range of from 11.2 MHz to 200 MHz, and it can be

programmed to spot frequencies over a continuous frequency

range of 200 MHz and 637.5 MHz, with only a few small gaps.

Table 19. Divider Ratio Setting Registers

Divider

I2C Registers

Parameter

Divide

Range

Channel 0 VCO divider

ADV0[7:5]

2 to 6

Channel 1 VCO divider

ADV1[7:5]

2 to 6

Channel 2 VCO divider

BDV0[7:5]

2 to 6

Channel 3 VCO divider

BDV1[7:5]

2 to 6

Channel 0 output divider

ADV0[4:0]

1 to 321

Channel 1 output divider

ADV1[4:0]

1 to 321

Channel 2 output divider

BDV0[4:0]

1 to 321

Channel 3 output divider

BDV1[4:0]

1 to 321

1 Set to 00000 for divide by 32.

Asserting the SyncCh01 or SyncCh23 bits (Register ADV2[0]

or Register BDV2[0]) allows each PLL output channel to use a

common VCO divider. This feature allows the OUT0/OUT1 and

OUT2/OUT3 output ports to have minimal skew when their

relative output channel divide ratio is an integer multiple.

Duty-cycle correction circuitry ensures that the output duty cycle

remains at 50%.

V0[2:0]

D0[4:0]

OUT0

OUTPUT

DIVIDER

VCO

DIVIDER

V1[2:0]

D1[4:0]

OUT1

OUTPUT

DIVIDER

VCO

DIVIDER

VCO

V2[2:0]

D2[4:0]

OUT2

OUTPUT

DIVIDER

VCO

DIVIDER

V3[2:0]

D3[4:0]

OUT3

OUTPUT

DIVIDER

VCO

DIVIDER

VCO

Figure 35. Output Channel Divider Signal Path

OUTPUTS

Each output port can be individually configured as either

differential LVPECL, differential LVDS, or two single-ended

LVCMOS clock outputs. The simplified equivalent circuit of the

LVDS outputs is shown in Figure 36.

3.5mA

OUTxP

OUTxN

Figure 36. LVDS Outputs Simplified Equivalent Circuit

The simplified equivalent circuit of the LVPECL outputs is

shown in Figure 37.

3.3V

OUTxP

OUTxN

GND

Figure 37. LVPECL Outputs Simplified Equivalent Circuit

Output channels (consisting of a VCO divider, output divider, and

an output buffer) can be individually powered down to save power.

Setting PDCH1 (Register BP0[1]) and PDCH3 (Register DR1[7])

powers down the respective channel. Setting PDCH0 (Register

BP0[0]) powers down both Channel 0 and Channel 1. Setting

PDCH2 (Register DR1[6]) powers down both Channel 2 and

Channel 3.

Output buffer combinations of LVDS, LVPECL, and CMOS can be

selected by setting DR1[5:0] as is shown in Table 20 and Table 21.

Table 20. PLL1 Output Driver Format Control Bits,

FORMAT1 (PLL1)

OUT1P/OUT1N

OUT0P/OUT0N

000

LVPECL

001

LVDS

010

2 × CMOS

LVPECL

011

2 × CMOS

100

2 × CMOS

LVDS

101

LVPECL

LVDS

110

LVPECL

2 × CMOS

1111

2 × CMOS

1 This indicates that the CMOS outputs are in phase; otherwise, they are in

antiphase.

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