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AD9577BCPZ-R7 数据表(PDF) 15 Page - Analog Devices

部件名 AD9577BCPZ-R7
功能描述  Clock Generator with Dual PLLs, Spread Spectrum, and Margining
PDF  44 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9577BCPZ-R7 数据表(HTML) 15 Page - Analog Devices

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Data Sheet
AD9577
Rev. A | Page 15 of 44
CRYSTAL OSCILLATOR
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CRYSTAL SPECIFICATION
Fundamental mode
Frequency
19.44
25
27
MHz
Reference divider, R = 1, only
ESR
50
Ω
Load Capacitance
14
pF
Phase Noise
−135
dBc/Hz
1 kHz offset
Stability
−50
+50
ppm
REFERENCE INPUT
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUT (REFCLK)
Input Frequency
19.44
25
27
MHz
Reference divider, R = 1
38.88
50
54
MHz
Reference divider, R = 2
Input High Voltage
2.0
V
Input Low Voltage
0.8
V
Input Current
−1.0
+1.0
µA
Input Capacitance
2
pF
CONTROL PINS
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT CHARACTERISTICS
SSCG, MAX_BW, and MARGIN
SSCG, MAX_BW, and MARGIN have a 30 kΩ internal
pull-down resistor
Logic 1 Voltage
2.0
V
Logic 0 Voltage
0.8
V
Logic 1 Current
240
µA
Logic 0 Current
40
µA
REFSEL
REFSEL has a 30 kΩ internal pull-up resistor
Logic 1 Voltage
2.0
V
Logic 0 Voltage
0.8
V
Logic 1 Current
70
µA
Logic 0 Current
240
µA
I2C DC CHARACTERISTICS
LVCMOS; the SCL and SDA pins only, see Figure 48
Input Voltage High
0.7 Vcc
V
Input Voltage Low
0.3 Vcc
V
Input Current
−10
+10
µA
VIN = 0.1 VCC or VIN = 0.9 VCC
Output Low Voltage
0.4
V
VOL with a load current of IOL = 3.0 mA
I2C TIMING CHARACTERISTICS
LVCMOS; the SCL and SDA pins only, see Figure 48
SCL Clock Frequency
400
kHz
SCL Pulse Width High
High, tHIGH
600
ns
Low, tLOW
1300
ns
Start Condition
Hold Time, tHD; STA
600
ns
Setup Time, tSU; STA
600
ns
Data
Setup Time, tSU; DAT
100
ns
Hold Time, tHD; DAT
300
ns
Stop Condition Setup Time, tSU; STO
600
ns
Bus Free Time Between a Stop and a Start, tBUF
1300
ns



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