AD9577BCPZ-R7 datasheet(14/44 Pages) AD

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AD9577

Data Sheet

Rev. A | Page 14 of 44

POWER

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER SUPPLY

3.0

3.3

3.6

LVPECL POWER DISSIPATION

1235

1490

Typical part configuration, both PLLs enabled for integer-N operation,

fOUT0 = 156.25 MHz, fOUT1 = 125 MHz, fOUT2 = 100 MHz, fOUT3 = 33.33 MHz,

Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,

D3 = 18, 25 MHz crystal used, load is 200 Ω to GND at output pins, then

ac-coupled to 50 Ω terminated measurement equipment

1270

1530

Worst-case part configuration, PLL2 in fractional-N mode, with SSCG

enabled, fOUT0 = 379.16 MHz, fOUT1 = 379.16 MHz, fOUT2 = 359.33 MHz,

fOUT3 = 359.33 MHz, Na = 91, V0 = 3, D0 = 2, V1 = 3, D1 = 2, Nb = 86,

V2 = 3, D2 = 2, V3 = 3, D3 = 2, FRAC = 300, MOD = 1250, CkDiv = 5,

NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,

25 MHz crystal used, load is 200 Ω to GND at output pins, then

ac-coupled to 50 Ω terminated measurement equipment

LVDS POWER DISSIPATION

1020

1200

Typical part configuration, both PLLs enabled for integer-N operation,

fOUT0 = 156.25 MHz, fOUT1 = 125 MHz, fOUT2 = 100 MHz, fOUT3 = 33.33 MHz,

Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,

D3 = 18, 25 MHz crystal used, load ac-coupled to measurement

equipment that provides 100 Ω differential input termination

1085

1290

Worst-case part configuration, PLL2 in fractional-N mode, with SSCG

enabled, fOUT0 = 379.16 MHz, fOUT1 = 379.16 MHz, fOUT2 = 359.33 MHz,

fOUT3 = 359.33 MHz, Na = 91, V0 = 3, D0 = 2, V1 = 3, D1 = 2, Nb = 86,

V2 = 3, D2 = 2, V3 = 3, D3 = 2, FRAC = 300, MOD = 1250, CkDiv = 5,

NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,

25 MHz crystal used, load ac-coupled to measurement equipment

that provides 100 Ω differential input termination

CMOS POWER DISSIPATION

1065

1380

Typical part configuration, both PLLs enabled for integer-N operation,

fOUT0 = 156.25 MHz, fOUT1 = 125 MHz, fOUT2 = 100 MHz, fOUT3 = 33.33 MHz,

Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,

D3 = 18, 25 MHz crystal used, eight single-ended outputs active,

CLOAD = 5 pF

1190

1510

Worst-case part configuration, PLL2 in fractional-N mode, with SSCG

enabled, fOUT0 = 189.58 MHz, fOUT1 = 189.58 MHz, fOUT2 = 179.66 MHz,

fOUT3 = 179.66 MHz, Na = 91, V0 = 3, D0 = 4, V1 = 3, D1 = 4, Nb = 86,

V2 = 3, D2 = 4, V3 = 3, D3 = 4, FRAC = 300, MOD = 1250, CkDiv = 5,

NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,

25 MHz crystal used, eight single-ended outputs active, CLOAD = 5 pF

POWER CHANGES

Reduction in power due to turning off a channel of one VCO divider,

one output divider, and one output buffer; data for Channel 1, with

typical part configuration, both PLLs enabled for integer-N operation,

fOUT0 = 156.25 MHz, fOUT1 = 125 MHz, fOUT2 = 100 MHz, fOUT3 = 33.33 MHz,

Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,

D3 = 18, 25 MHz crystal used

Power-Down 1 LVPECL Channel

160

205

Load 200 Ω to GND at output pins, and ac-coupled to 50 Ω terminated

measurement equipment

Power-Down 1 LVDS Channel

105

155

Load ac-coupled to measurement equipment that provides 100 Ω

differential input termination

Power-Down 1 CMOS Channel

130

170

Eight single-ended outputs active, CLOAD = 5 pF

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