AD9577BCPZ-R7 datasheet(39/44 Pages) AD

39 / 44 page

Data Sheet

AD9577

Rev. A | Page 39 of 44

Table 30. Internal Register Map

Name

R/W

Addr

0x40

EnI2C

0x1F

NewAcq

BP0

0x11

Bleed

PDCH1

PDCH0

AF0

0x18

Na[5:0], PLL1 feedback divider ratio

BF3

0x1C

Nb[5:0], PLL2 feedback divider ratio

BF0

0x19

FRAC[11:4], SDM fractional word

BF1

0x1A

FRAC[3:0], SDM fractional word

MOD[11:8], SDM modulus

BF2

0x1B

MOD[7:0], SDM modulus

ABF0

0x1D

PD_SDM

ADV0

0x22

V0[2:0], Channel 0 VCO divider

D0[4:0], Channel 0 output divider value

ADV1

0x23

V1[2:0], Channel 1 VCO divider

D1[4:0], Channel 1 output divider value

ADV2

0x24

SyncCh01

BDV0

0x25

V2[2:0], Channel 2 VCO divider

D2[4:0], Channel 2 output divider value

BDV1

0x26

V3[2:0], Channel 3 VCO divider

D3[4:0], Channel 3 output divider value

BDV2

0x27

SyncCh23

BS1

0x2A

FracStep[7:0], SSCG fractional step size

BS2

0x2B

NumSteps[8:1], number of fractional word increments/decrements per half triangular-wave cycle

BS3

0x2C

NumSteps[0]

CkDiv[6:0], reference divider output is divided by this integer to determine SSCG update rate

AM0

0x30

Na[5:0], PLL1 feedback divider ratio divider; MARGIN = 1

AM1

0x31

V0[2:0], Channel 0 VCO divider;

MARGIN = 1

D0[4:0], Channel 0 output divider value; MARGIN = 1

AM2

0x32

V1[2:0], Channel 1 VCO divider;

MARGIN = 1

D1[4:0], Channel 1 output divider value; MARGIN = 1

BM0

0x33

Nb[5:0], PLL2 feedback divider ratio divider; MARGIN = 1

BM1

0x34

FRAC[11:4], SDM fractional word; MARGIN = 1

BM2

0x35

FRAC[3:0], SDM fractional word; MARGIN = 1

MOD[11:8], SDM modulus; MARGIN = 1

BM3

0x36

MOD[7:0], SDM modulus; MARGIN = 1

BM4

0x37

V3[2:0], Channel 3 VCO divider;

MARGIN = 1

D3[4:0], Channel 3 output divider value; MARGIN = 1

BM5

0x38

V2[2:0], Channel 2 VCO divider;

MARGIN = 1

D2[4:0], Channel 2 output divider value; MARGIN = 1

DR1

0x3A

PDCH3

PDCH2

FORMAT2[2:0], output format selection

for PLL2 (see

Table 21)

FORMAT1[2:0], output format selection for

PLL1 (see

Table 20)

DR2

0x3B

PDRefOut

0x3D

PDPLL1, power-

down PLL1

PDPLL2, power-

down PLL2

R; 0 =

divide by 1

AD9577BCPZ-R7 数据表(PDF) 39 Page - Analog Devices

AD9577BCPZ-R7 数据表(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载

链接网址

AD9577BCPZ-R7 数据表(PDF) 39 Page - Analog Devices

AD9577BCPZ-R7 数据表(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表 下载

链接网址

数据表下载