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AD9119BBCZ 数据表(PDF) 4 Page - Analog Devices |
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AD9119BBCZ 数据表(HTML) 4 Page - Analog Devices |
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4 / 66 page  AD9119/AD9129 Data Sheet Rev. B | Page 4 of 66 LVDS DIGITAL SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. LVDS drivers and receivers are compatible with the IEEE Standard 1596.3-1996, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit LVDS DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N, P0_D[13:0]P, P0_D[13:0]N, FRM_P, FRM_N) Px_DxP = VIA, Px_DxN = VIB Input Voltage Range VIA, VIB 825 1575 mV Input Differential Threshold VIDTH −100 +100 mV Input Differential Hysteresis VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance RIN 80 120 Ω LVDS Input Rate 1425 MSPS Input Capacitance 1.2 pF LVDS CLOCK INPUTS (DCI_P, DCI_N) DCI_P = VIA, DCI_N = VIB Input Voltage Range VIA, VIB 825 1575 mV Input Differential Threshold VIDTH −225 +225 mV Input Differential Hysteresis VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance RIN 80 120 Ω Maximum Clock Rate 712.5 MHz LVDS CLOCK OUTPUTS (DCO_P, DCO_N) DCO_P = VOA, DCO_N = VOB, 100 Ω termination Output Voltage High VOA, VOB 1375 mV Output Voltage Low VOA, VOB 1025 mV Output Differential Voltage |VOA|, |VOB| Register 0x7C[7:6] = 01b (default) 200 225 250 mV Output Offset Voltage VOS 1150 1250 mV Output Impedance, Single-Ended RO 80 100 120 Ω RO Mismatch Between A and B ∆RO 10 % Change in |VOD| Between Setting 0 and Setting 1 |∆VOD| 25 mV Change in VOS Between Setting 0 and Setting 1 ∆VOS 25 mV Output Current Driver Shorted to Ground ISA, ISB 20 mA Drivers Shorted Together ISAB 4 mA Power-Off Output Leakage |IXA|, |IXB| 10 µA Maximum Clock Rate 712.5 MHz HSTL DIGITAL SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. HSTL receiver levels are compatible with the EIA/JEDEC JESD8-6 standard, unless otherwise noted. Table 3. Parameter Symbol Test Comments/Conditions Min Typ Max Unit HSTL DATA INPUTS (P1_D[13:0]P, P1_D[13:0]N, P0_D[13:0]P, P0_D[13:0]N, FRM_P, FRM_N) Px_DxP = VIA, Px_DxN = VIB Common-Mode Input Voltage Range VIA, VIB 0.68 0.9 V Differential Input Voltage 200 mV Receiver Differential Input Impedance RIN 80 120 Ω HSTL Input Rate 1425 MSPS Input Capacitance 1.2 pF HSTL CLOCK INPUT (DCI_P, DCI_N) DCI_P = VIA, DCI_N = VIB Common-Mode Input Voltage Range VIA, VIB 0.68 0.9 mV Differential Input Voltage 450 mV Receiver Differential Input Impedance RIN 80 120 Ω Maximum Clock Rate 712.5 MHz |
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