AD9119BBCZ datasheet(59/66 Pages) AD

59 / 66 page

Data Sheet

AD9119/AD9129

Rev. B | Page 59 of 66

Data Receiver Control 1 Register

Address: 0x0B, Reset: 0x29, Name: Data Ctrl 1

Table 27. Bit Descriptions for Data Ctrl 1

Bits

Bit Name

Description

Reset

Access

Warn clear

1: clears data receiver warning bit

R/W

Lock delay divider

1: long delay

0: short delay

R/W

[5:4]

Controller clock divider

00: DCI/4

01: DCI/16

10: DCI/64

11: DCI/512

0x2

R/W

[3:0]

Delay line middle set

Sets nominal delay line delay

0x9

R/W

Data Receiver Control 2 Register

Address: 0x0C, Reset: 0x23, Name: Data Ctrl 2

Table 28. Bit Descriptions for Data Ctrl 2

Bits

Bit Name

Description

Reset

Access

Reserved

R/W

DCO enable

1: enables DCO output driver

R/W

[5:3]

Maximum delay set

Sets maximum delay line delay (larger number = longer delay line)

0x2

R/W

[2:0]

Minimum delay set

Sets minimum delay line delay (larger number = smaller delay line)

0x3

R/W

Data Receiver Control 3 Register

Address: 0x0D, Reset: 0x04, Name: Data Ctrl 3

Table 29. Bit Descriptions for Data Ctrl 3

Bits

Bit Name

Description

Reset

Access

[7:3]

Reserved

Reserved.

0x00

[2:1]

Duty correction BW set

Sets the bandwidth of the duty cycle correction circuit.

00: highest BW.

01: higher BW.

10: lower BW.

11: lowest BW.

0x2

R/W

Reserved

R/W

Data Receiver Status 0 Register

Address: 0x0E, Reset: 0x00, Name: Data Status 0

Table 30. Bit Descriptions for Data Status 0

Bits

Bit Name

Description

Reset

Access

DLL lock

1: DLL lock

DLL warning

1: DLL near beginning/end of delay line

DLL delay line start warning

1: DLL at beginning of delay line

DLL delay line end warning

1: DLL at end of delay line

DLL correct phase

1: data is sampled on correct phase

0: data is sampled on incorrect phase.

DCI on

1: user has provided a clock > 100 MHz

DLL lock phase

1: DLL is locked on negative half of DCI.

0: DLL is locked on positive half of DCI

DLL running

1: closed loop DLL attempting to lock

0: delay fixed at middle of delay line

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AD9119BBCZ 数据表(PDF) 59 Page - Analog Devices

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