AD9119BBCZ datasheet(58/66 Pages) AD

58 / 66 page

AD9119/AD9129

Data Sheet

Rev. B | Page 58 of 66

Interrupt Status Register1

Address: 0x06, Reset: 0x00, Name: IRQ Request 1

Table 23. Bit Descriptions for IRQ Request 1

Bits

Bit Name

Description

Reset

Access

Reserved

R/W

AED pass interrupt status

Indicates that the AED logic has captured eight valid samples

R/W

AED fail interrupt status

Indicates that the AED logic has detected a miscompare

R/W

SED fail interrupt status

Indicates that the SED logic has detected a miscompare

R/W

Parity error falling edge status

Indicates a parity fault due to data captured on the falling edge

R/W

Parity error rising edge status

Indicates a parity fault due to data captured on the rising edge

R/W

Reserved

R/W

Reserved

R/W

Frame Pin Usage Register

Address: 0x07, Reset: 0x00, Name: Frame Pin Usage

Table 24. Bit Descriptions for Frame Pin Usage

Bits

Bit Name

Description

Reset

Access

Reserved

R/W

Reserved

R/W

ParUsage

1: FRM_x pin is in parity mode, and parity is enabled

Note that parity must be enabled, and the type must be chosen in Register 0x5C[7:6]

FrmUsage

1: FRM_x pin is in frame mode and enable pin framing (Register 0x11[5] = 1b) is

enabled

Reserved

[1:0]

FRM_x pin usage mode

3: reserved

2: frame

1: parity

0: no effect

0x0

R/W

Reserved_0 Register

Address: 0x08, Reset: 0x58, Name: Reserved_0

Table 25. Bit Descriptions for Reserved_0

Bits

Bit Name

Description

Reset

Access

[7:0]

Reserved

Must keep default (reset) value; reserved

0x58

Data Receiver Control 0 Register

Address: 0x0A, Reset: 0x40, Name: Data Ctrl 0

Table 26. Bit Descriptions for Data Ctrl 0

Bits

Bit Name

Description

Reset

Access

DLL enable

1: enables DLL

0: disables DLL

R/W

Duty cycle correction enable

1: enables duty cycle correction

0: disables duty cycle correction

R/W

Reserved

R/W

Reserved

R/W

[3:0]

Phase offset

Locked phase = 90° ± n × 11.25°, where n is the 4-bit signed magnitude number

0x0

R/W

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