AD9119BBCZ datasheet(49/66 Pages) AD

49 / 66 page

Data Sheet

AD9119/AD9129

Rev. B | Page 49 of 66

ANALOG INTERFACE CONSIDERATIONS

ANALOG MODES OF OPERATION

The AD9119/AD9129 use the quad-switch architecture shown in

Figure 143. Only one pair of switches is enabled during a half-clock

cycle, thus requiring each pair to be clocked on alternative clock

edges. A key benefit of the quad-switch architecture is that it masks

the code-dependent glitches that occur in the conventional two-

switch DAC architecture.

VG1

VSSA

IOUTP

IOUTN

VG1

VG2 VG3

VG4

DACCLK_x

CLK

LATCHES

Px_D[13:0]x

VG2

VG3

VG4

Figure 143. Quad-Switch Architecture

In two-switch architecture, when a switch transition occurs and

D1 and D2 are in different states, a glitch occurs. But, if D1 and

D2 happen to be at the same state, the switch transitions, and no

glitches occur. This code-dependent glitching causes an increased

amount of distortion in the DAC. In quad-switch architecture

(no matter what the codes are), there are always two switches

that are transitioning at each half-clock cycle, thus eliminating

the code-dependent glitches but, in the process, creating a constant

glitch at 2 × DACCLK. For this reason, a significant clock spur

at 2 × fDACCLK is evident in the DAC output spectrum.

INPUT

DATA

DACCLK_x

TWO-SWITCH

DAC OUTPUT

FOUR-SWITCH

DAC OUTPUT

(NORMAL MODE)

D9 D10

Figure 144. Two-Switch and Quad-Switch DAC Waveforms

As a consequence of the quad-switch architecture enabling

updates on each half-clock cycle, it is possible to operate that

DAC core at 2× the DACCLK rate if new data samples are latched

into the DAC core on both the rising and falling edge of the

DACCLK. This notion serves as the basis when operating the

AD9119/AD9129 in either Mix-Mode or with the 2× interpo-

lation filter enabled. In each case, the DAC core is presented

with new data samples on each clock edge, albeit in Mix-Mode;

the falling edge sample is simply the complement of the rising

edge sample value.

When Mix-Mode is used, the output is effectively chopped at

the DAC sample rate. This has the effect of reducing the power

of the fundamental signal while increasing the power of the

images centered around the DAC sample rate, thus improving

the dynamic range of these images.

INPUT

DATA

DACCLK_x

FOUR-SWITCH

DAC OUTPUT

(

fS MIX-MODE)

–D6

–D7

–D8

–D9

–D10

D10

–D1

–D2

–D3

–D4

–D5

D9 D10

Figure 145. Mix-Mode Waveform

This ability to change modes provides the user the flexibility to

place a carrier anywhere in the first three Nyquist zones, depending

on the operating mode selected. Switching between baseband

and Mix-Mode reshapes the sinc roll-off inherent at the DAC

output. In baseband mode, the sinc null appears at fDACCLK

because the same sample latched on the rising clock edge is also

latched again on the falling clock edge, thus resulting in the

same ubiquitous sinc response of a traditional DAC. In Mix-

Mode, the complement sample of the rising edge is latched on

the falling edge, therefore pushing the sinc null to 2 × fDACCLK.

Figure 146 shows the ideal frequency response of both modes

with the sinc roll-off included.

NORMALIZED FREQUENCY RELATIVE TO

fDACCLK (Hz)

1.50

1.25

1.00

0.75

0.50

0.25

–35

–30

–25

–20

–15

–10

–5

FIRST

NYQUIST ZONE

SECOND

NYQUIST ZONE

THIRD

NYQUIST ZONE

MIX-MODE

BASEBAND

MODE

Figure 146. Sinc Roll-Off for Baseband Mode and Mix-Mode Operation

The quad-switch can be configured via SPI (Register 0x19, Bit 0)

to operate in either baseband mode (0b) or Mix-Mode (1b).

AD9119BBCZ 数据表(PDF) 49 Page - Analog Devices

AD9119BBCZ 数据表(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载

链接网址

AD9119BBCZ 数据表(PDF) 49 Page - Analog Devices

AD9119BBCZ 数据表(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表 下载

链接网址

数据表下载