AD9119BBCZ datasheet(39/66 Pages) AD

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Data Sheet

AD9119/AD9129

Rev. B | Page 39 of 66

LVDS DATA PORT INTERFACE

The AD9119/AD9129 can operate with input data rates of up to

2.85 GSPS. A source synchronous LVDS interface is used

between the host and the AD9119/AD9129 to achieve these high

data rates, while simplifying the interface. As shown in Figure

129, the host feeds the AD9119/AD9129 with de-interleaved

input data into two 11-bit/14-bit LVDS data ports (P0_DxP,

P0_DxN and P1_DxP, P1_DxN) at ½ the DAC clock rate (that

is, fDACCLK/2). Along with the input data, the host provides an

embedded DDR data clock input (DCI_x) at fDACCLK/4.

A DLL circuit that is designed to operate with DCI clock rates

of between 350 MHz and 712.5 MHz is used to generate a phase

shifted version of DCI, called the data sampling clock (DSC),

to register the input data on both the rising and falling edges.

As shown in Figure 130, the DCI clock edges must be coincident

with the data bit transitions with minimum skew and jitter. The

nominal sampling point of the input data occurs in the middle

of the DCI clock edges because this point corresponds to the

center of the data eye. This is also equivalent to a nominal phase

shift of 90°of the DCI clock.

The data timing requirements are defined by a minimum data

valid margin that is dependent on the data clock input skew,

input data jitter, and the variations of the DLL delay line across

delay settings. This margin is defined by subtracting from the

data period any data skew, data jitter, and the keep-out window

(KOW) that is defined by the sum of the set and hold times, as

follows:

tDATA VALID MARGIN = tDATA PERIOD − tDATA SKEW − tDATA JITTER − (tH + tS)

The keep-out window, which is the sum of the set and hold times,

is the area where data transitions should not occur. The timing

margin allows tuning of the DLL delay setting, either automatically

or in manual mode (see Figure 130).

Figure 130 shows that the ideal location for the DSC signal is 90°

out of phase from the DCI input. However, due to skew of the DCI

relative to the data, it may be necessary to change the DSC phase

offset to sample the data at the center of its eye diagram. The

sampling instance can be varied in discrete increments by offsetting

the nominal DLL phase shift value of 90° via Register 0x0A,

Bits[3:0]. The following equation defines the phase offset

relationship:

Phase Offset = 90° ± n × 11.25°, |n| < 8

DCI

DCO

CLOCK

DISTRIBUTION

DELAY

LOCK

LOOP

AD9129

HOST

PROCESSOR

14 × 2

1 × 2

fDATA = fDACCLK/2

fDCO = fDACCLK/4

fDCI = fDACCLK/4

fDACCLK

EVEN DATA

SAMPLES

ODD DATA

SAMPLES

OPTIONAL PARITY

COMBINED

ODD/EVEN

PARITY BIT

Figure 129. Recommended Digital Interface Between the AD9119/AD9129 and the Host Processor

INPUT DATA[13:0]

DCI

DLL PHASE

DELAY

tDATA PERIOD

tDATA SKEW

tDSC SETUP AND HOLD

tDATA JITTER

DATA SAMPLE CLOCK

DATA EYE

Figure 130. LVDS Data Port Timing Requirements

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