Data Sheet

SSM2517

Rev. B | Page 5 of 16

PDM INTERFACE DIGITAL TIMING SPECIFICATIONS

Table 3.

Limit

Parameter

Unit

Description

44

ns

Valid data start time1

7

ns

Valid data end time1

clock edge because the SSM2517 does this internally to ensure good timing margins. The data line should remain constant during the valid sample period illustrated

in Figure 2; it may transition at any other time. Timing is measured from 70% of VDD on the rising edge or 30% VDD on the falling edge.

Timing Diagram

PCLK

PDAT

VALID LEFT SAMPLE

VALID LEFT SAMPLE

VALID RIGHT SAMPLE

Figure 2. PDM Interface Timing