Data Sheet

SSM2517

Rev. B | Page 13 of 16

THEORY OF OPERATION

MASTER CLOCK

The SSM2517 requires a clock present at the PCLK input pin.

This clock must be fully synchronous with the incoming digital

audio on the serial interface. The clock frequencies must fall

into one of these ranges: 1.84 MHz to 3.23 MHz or 3.68 MHz

to 6.46 MHz.

POWER SUPPLIES

The SSM2517 requires two power supplies: PVDD and VDD.

PVDD

The PVDD pin supplies power to the full-bridge power stage

of a MOSFET and its associated drive, control, and protection

circuitry. It also supplies power to the digital-to-analog converter

(DAC) and to the Class-D PDM modulator. PVDD can operate

from 2.5 V to 5.5 V and must be present to obtain audio output.

Lowering the supply voltage of PVDD results in lower maximum

output power and, therefore, lower power consumption.

VDD

The VDD pin provides power to the digital logic circuitry.

VDD can operate from 1.62 V to 3.6 V and must be present

to obtain audio output. Lowering the supply voltage of VDD

results in lower power consumption but does not affect audio

performance.

POWER CONTROL

On device power-up, PVDD must first be applied to the device,

which latches in the designated GAIN_FS pin functionality.

The SSM2517 contains a smart power-down feature. When

enabled, the smart power-down feature looks at the incoming

digital audio and, if it receives the PDM stop condition of at

least 128 repeated 0xAC bytes (1024 clock cycles), it places the

SSM2517 in the standby state. In the standby state, the PCLK can

be removed, resulting in a full power-down state. This state is

the lowest power condition possible. When the PCLK is turned

on again and a single non-stop condition input is received, the

SSM2517 leaves the full power-down state and resumes normal

operation.

POWER-ON RESET/VOLTAGE SUPERVISOR

The SSM2517 includes an internal power-on reset and voltage

supervisor circuit. This circuit provides an internal reset to all

circuitry whenever PVDD or VDD is substantially below the

nominal operating threshold. This circuit simplifies supply

sequencing during initial power-on.

The circuit also monitors the power supplies to the SSM2517. If

the supply voltages fall below the nominal operating threshold,

this circuit stops the output and issues a reset. This ensures that

no damage occurs due to low voltage operation and that no

pops can occur under nearly any power removal condition.

SYSTEM GAIN/INPUT FREQUENCY

The GAIN_FS pin is used to set the internal gain and filtering

configuration for different sample rates of the SSM2517. This pin

can be set to one of four states by connecting the pin to PVDD or

PGND (see Table 7). The internal gain and filtering can also be

set via PDM pattern control, allowing these settings to be modi-

fied during operation (see the PDM Pattern Control section).

Table 7. GAIN_FS Function Descriptions

Device Setting

GAIN Pin Configuration

Pull up to PVDD with a 47 kΩ

resistor

Pull down to PGND with a 47 kΩ

resistor

Pull up to PVDD

Pull down to PGND

The SSM2517 has an internal analog gain control such that

when GAIN_FS is tied to PGND or PVDD via a 47 kΩ resistor

(5 V gain setting), a −6.02 dBFS PDM input signal results in

an amplifier output voltage of 5 V peak. This setting should

produce optimal noise performance when PVDD = 5 V.

When the GAIN_FS pin is tied directly to PGND or PVDD, the

gain is adjusted so that a −6.02 dBFS PDM input signal results

in an amplifier output voltage of 3.6 V peak. This setting should

produce optimal noise performance when PVDD = 3.6 V.

in each of these cases. Selection of the sample rate is also set via

the GAIN_FS pin (see Table 7).

should be used only when overall system noise performance is

limited by the source modulator.