Data Sheet

SSM2517

Rev. B | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

BALL A1

CORNER

A

3

2

1

B

C

OUT+

PGND

PVDD

OUT–

LRSEL

VDD

PCLK

PDAT

GAIN_FS

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Function

Description

A1

OUT+

Output

Noninverting Output.

A2

PVDD

Supply

Amplifier Power, 2.5 V to 5.5 V.

A3

PGND

Ground

Amplifier Ground.

B1

OUT−

Output

Inverting Output.

B2

LRSEL

Input

Left/Right Channel Select. Pull up to VDD for right channel; tie to ground for left channel.

B3

VDD

Supply

Digital Power, 1.62 V to 3.6 V.

C1

PCLK

Input

PDM Interface Master Clock.

C2

PDAT

Input

PDM Data Signal.

C3

GAIN_FS

Input

Gain and Sample Rate Selection Pin.