SSM2517

Data Sheet

Rev. B | Page 14 of 16

PDM PATTERN CONTROL

The SSM2517 has a simple control mechanism that can set the

part for low power states and control functionality. This is

accomplished by sending a repeating 8-bit pattern to the device.

Different patterns set different functionality (see Table 8).

Any pattern must be repeated a minimum of 128 times. The

part is automatically muted when a pattern is detected so that

a pattern can be set while the part is operational without a

pop/click due to pattern transition.

All functionality set via patterns returns to its default value after

a clock-loss power-down.

Table 8. PDM Watermarking Pattern Control Descriptions

Pattern

Control Description

0xAC

Power-down. All blocks off except for PDM interface.

Normal start-up time.

0xD8

Gain optimized for PVDD = 5 V operation.

Overrides GAIN_FS pin setting.

0xD4

Gain optimized for PVDD = 3.6 V operation.

Overrides GAIN_FS pin setting.

0xD2

Gain optimized for PVDD = 2.5 V operation.

Overrides GAIN_FS pin setting.

0xD1

0xE1

Ultralow EMI mode.

0xE2

Half clock cycle pulse mode for power savings.

0xE4

EMI NOISE

The SSM2517 uses a proprietary modulation and spread-

spectrum technology to minimize EMI emissions from the

device. For applications that have difficulty passing FCC

Class-B emission tests, the SSM2517 includes a modulation

select mode (ultralow EMI emissions mode) that significantly

reduces the radiated emissions at the Class-D outputs, particu-

larly above 100 MHz. This mode is enabled by activating PDM

Watermarking Pattern 0xE1 (see Table 8).

OUTPUT MODULATION DESCRIPTION

The SSM2517 uses three-level, Σ-Δ output modulation. Each

output can swing from PGND to PVDD and vice versa. Ideally,

when no input signal is present, the output differential voltage is

0 V because there is no need to generate a pulse. In a real-world

situation, noise sources are always present.

Due to this constant presence of noise, a differential pulse is

generated, when required, in response to this stimulus. A small

amount of current flows into the inductive load when the differ-

ential pulse is generated.

Most of the time, however, the output differential voltage is 0 V,

due to the Analog Devices, Inc., three-level, Σ-Δ output modula-

tion. This feature ensures that the current flowing through the

inductive load is small.

When the user wants to send an input signal, an output pulse

(OUT+ and OUT−) is generated to follow the input voltage.

The differential pulse density (VOUT) is increased by raising

the input signal level. Figure 30 depicts three-level, Σ-Δ output

modulation with and without input stimulus.

OUTPUT > 0V

+5V

0V

OUT+

+5V

0V

OUT–

+5V

0V

VOUT

OUTPUT < 0V

+5V

0V

OUT+

+5V

0V

OUT–

0V

–5V

VOUT

OUTPUT = 0V

OUT+

+5V

0V

+5V

0V

OUT–

+5V

–5V

0V

VOUT

Figure 30. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus