PDM Digital Input, Mono

2.4 W Class-D Audio Amplifier

Data Sheet

SSM2517

Rev. B

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FEATURES

Filterless digital Class-D amplifier

Pulse density modulation (PDM) digital input interface

2.4 W into 4 Ω load and 1.38 W into 8 Ω load at 5.0 V supply

with <1% total harmonic distortion plus noise (THD + N)

Available in 9-ball, 1.5 mm × 1.5 mm, 0.5 mm pitch WLCSP

92% efficiency into 8 Ω at full scale

Output noise: 43 μV rms at 3.6 V, A-weighted

THD + N: 0.035% at 1 kHz, 100 mW output power

PSRR: 85 dB at 217 Hz, input referred with dither input

Quiescent power consumption: 10.4 mW

(VDD = 1.8 V, PVDD = 3.6 V, 8 Ω + 33 μH load)

Pop-and-click suppression

Configurable with PDM pattern inputs

Short-circuit and thermal protection with autorecovery

Smart power-down when PDM stop condition

or no clock input detected

DC blocking high-pass filter and static input dc protection

User-selectable ultralow EMI emissions mode

Power-on reset (POR)

Minimal external passive components

APPLICATIONS

Mobile handsets

GENERAL DESCRIPTION

The SSM2517 is a PDM digital input Class-D power amplifier

that offers higher performance than existing DAC plus Class-D

solutions. The SSM2517 is ideal for power sensitive applications,

such as mobile phones and portable media players, where system

noise can corrupt the small analog signal sent to the amplifier.

The SSM2517 combines an audio digital-to-analog converter

(DAC), a power amplifier, and a PDM digital interface on a single

chip. The integrated DAC plus analog Σ-Δ modulator architecture

enables extremely low real-world power consumption from

digital audio sources with excellent audio performance. Using

the SSM2517, audio can be transmitted digitally to the audio

amplifier, significantly reducing the effect of noise sources such as

GSM interference or other digital signals on the transmitted audio.

The SSM2517 is capable of delivering 2.4 W of continuous output

power with <1% THD + N driving a 4 Ω load from a 5.0 V supply.

The SSM2517 features a high efficiency, low noise modulation

scheme that requires no external LC output filters. The closed-loop,

three-level modulator design retains the benefits of an all-digital

amplifier, yet enables very good PSRR and audio performance. The

modulation continues to provide high efficiency even at low output

power and has an SNR of 96 dB. Spread-spectrum pulse density

modulation is used to provide lower EMI-radiated emissions

compared with other Class-D architectures.

The SSM2517 has a four-state gain and sample frequency selection

pin that can select two different gain settings, optimized for 3.6 V

and 5 V operation. This same pin also controls the internal digital

sample rates to support both 3 MHz and 6 MHz PDM clock rates.

The SSM2517 has a micropower shutdown mode with a typical

shutdown current of 1 μA for both power supplies. Shutdown is

enabled automatically by gating input clock and data signals. A

standby mode can be entered by applying a designated PDM stop

condition sequence. The device also includes pop-and-click sup-

pression circuitry. This suppression circuitry minimizes voltage

glitches at the output when entering or leaving the low power

state, reducing audible noises on activation and deactivation.

The SSM2517 is specified over the industrial temperature range

of −40°C to +85°C. It has built-in thermal shutdown and output

short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm

wafer level chip scale package (WLCSP).

FUNCTIONAL BLOCK DIAGRAM

PDAT

VDD

POWER-ON

RESET

CLOCKING POWER

CONTROL

PCLK

GAIN_FS

LRSEL

OUT+

OUT–

PVDD

PGND

INPUT

INTERFACE

FILTERING/

DAC

Σ-∆

CLASS-D

MODULATOR

FULL-BRIDGE

POWER STAGE

SSM2517

Figure 1.