DA6512.003

2 December, 2016

20 (32)

2-WIRE SERIAL DATA INTERFACE (I2C BUS)

Conversion Result – Read Sequence

Table 13 presents a general control sequence for a

single register data read.

Table 13. MAS6512 I2C bus single register (address Ax) read sequence bits

S

AW

A

Ax

A

Sr

AR

A

Dx

N

P

Table 14 shows the control sequence for reading

the

16-bit

A/D

conversion

result

from

the

Conversion result registers. The LSB (DL) register

data read can follow right after the MSB register

data (DM) read since if the read sequence is

continued (not ended by a Stop bit P) the register

address is automatically incremented to point to the

next register.

Table 14. MAS6512 I2C bus MSB (first byte) and LSB (second byte) A/D conversion result read sequence

S

AW

A

AM

A

Sr

AR

A

DM

A

DL

N

P

4-WIRE SERIAL DATA INTERFACE (SPI BUS)

SPI bus communication is selected by setting XSPI

pin low.

SPI communication differs from I2C bus in the

following way. It requires four wires for bi-directional

communication since each line operates in one

direction only. Device selection is done by using

separate chip select XCS control lines instead of

using device address. Each SPI bus device has its

own XCS control line and a device is selected by

pulling its XCS line low (see figure 5 below). The

fourth wire in the SPI bus is the serial clock line,

SCLK. Data is transferred at rising edges of the

serial clock during which the data line should be

stable.

The selection between write or read access is done

by register address MSB bit A7 (see table 1

“Register and EEPROM data addresses”). In write

access bit A7 cleared (0) and in read access it is set

(1).

Figure 5 illustrates write access communication.

MAS6512 has an auto increment function which

means that if there are more than one data byte

transferred the additional data bytes are delivered to

following

register

addresses.

In

write

communication the MISO line is high impedance.

In SPI bus communication it is good to note that

setting XCS low activates the EEPROM memory

regardless of the XSPI setting and the device

consumes 20

A …30A current. To minimize

current consumption XCS should be set low only

during time periods when the device is used during

SPI communication.

XCS

SCK

SDA

MISO

MSB

LSB

Register Address Byte

MSB

LSB

Data Byte

High Z

Figure 5. SPI Protocol – Write Access (register address MSB bit A7=0)

SCLK

MOSI