DA6512.003

2 December, 2016

26 (32)

APPLICATION INFORMATION

VDD rise time < 1ms

Figure 9. MAS6512 configured for I2C bus communication

Note: MAS6512 has an effective ESD clamp protection structure that can be triggered if the VDD rises too fast.

For this reason it’s recommended to use a supply decoupling capacitor having a value of 100nF or higher to slow

down the VDD rise time.

Note: The voltage regulator output VREG does not require external capacitor as shown in figure 9. However if an

output capacitor is wanted to be used for extra filtering the capacitor value should not be higher than 6.8nF.

Figure 9 presents MAS6512 application circuit using I2C bus and when VDD rise time is guaranteed to be

always below internal POR circuit delay of 1ms. In case the VDD rise time can exceed 1ms see the next page

application information.

MISO

SDA/MOSI

SCL/SCLK

MUX

TEMP



CONTROL

I2C /

SPI

EEPROM

CLK

OSC

XCS

XSPI

EOC

XCLR

CS

CC

CR

VDD

GND

optional

MCU

optional

optional

VDD

GND

Cs

Cr

VREG

TEST

VREG

TEST1

TEST2

VDD

OSC

GND

VDD

4k7

4k7

GND

100n

NOTE: It is recommended to use the XCLR reset feature to solve unexpected error state conditions. In case VDD rise time can

exceed 1ms the device has to be kept in a reset during power up by using the XCLR pin. Violating this may risk EEPROM integrity.

If not used the XCLR pin can be left unconnected since it has internal pull up to VDD.