MT7697 datasheet(21/81 Pages) ETC2

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MT7697

Internet-of-Things Wireless Connectivity

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This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

MT7697 includes the memory protection unit (MPU) in Cortex-M4 MCU that provides memory

protection features. It can be used to detect unexpected memory access.

MT7697 also includes floating point unit (FPU) in Corxex-M4 process to support DSP related function.

2.4.2

Cache and Tightly Coupled Memory

MT7697 has a cache for Cortex-M4 to improve the efficiency of the code and data fetch from the

external flash. The only cacheable memory region is the external flash.

MT7697 also has a Tightly-Coupled-Memory (TCM), a zero-wait-state memory which is dedicated for

Cortex-M4 and can be accessed by Cortex-M4 exclusively. It is a memory space for the critical code

such as interrupt service routines which needs to be executed with minimum latency. The DMA

engines on AHB bus can’t access TCM.

The total size of memory of the cache and the TCM is 96KB. Four software-configurable options differ

in the size of cache, the size of TCM, and the cache associativity. The user can select the option which

maximizes the performance.

The cache system has the following features:



Configurable 1/2/4-way set associative (8KB/16KB/32KB)



Each way has 256 cache lines with 8-word link size



20-bit tag memory: 19-bit high address and 1-bit valid bit



2-bit dirty memory: each dirty bit identifies the dirtiness of half cache line

The size of SRAM is 96KB. It can be configured to the following configuration



96KB TCM, no cache



88KB TCM, 8KB cache (1 way, direct mapped)



80KB TCM, 16KB cache (2 way set-associative)



64KB TCM, 32KB cache (4 way set-associative)

The configuration setting and the memory configuration are shown in the following table.

Table 2-9. TCM and Cache Configuration

0x0153_0000[9:8]

Functional Description

Start Address

End Address

00b

96KB TCM, no cache

0x0010_0000

0x0011_7FFF

01b

88KB TCM, 8KB cache, direct mapped

0x0010_0000

0x0011_5FFF

10b

80KB TCM, 16KB cache, 2-way set-associative

0x0010_0000

0x0011_3FFF

11b

64KB TCM, 32KB cache, 4-way set associative

0x0010_0000

0x0010_FFFF

The cache controller provides the user ways to perform cache operations including invalidate

single/all cache lines as well as flush one/all cache lines.

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