MT7697 datasheet(25/81 Pages) ETC2

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MT7697

Internet-of-Things Wireless Connectivity

Page 25 of 81

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

Hardware Function

DMA Type

Radio (Wi-Fi)

Half size DMA x 1

UART (x2)

Virtual FIFO DMA x 4

I2S

Virtual FIFO DMA x 2

ADC

Virtual FIFO DMA x 1

I2C (x2)

Half size DMA x 4

SPI-M

Half size DMA x 2

Secure boot

Full size DMA x 1

Reserved

Full size DMA x 1, half size DMA x 3 and virtual FIFO DMA x 4.

The DMA provides two levels of scheduling scheme among all channels.

The 1st level scheduling follows the strict-priority scheme. All channels can be grouped into four

priority groups. Group one gets the highest priority, then group two, and so on.

The 2nd level scheduling follows the round-robin scheme. Every channel in the same priority group

has equal opportunity to use the bandwidth and was served sequentially.

The arbitration is done per AHB transaction. When one AHB transaction is finished, the scheduler will

follow the above mechanism to select the next DMA channel to serve.

2.4.6

General Purpose Timer

MT7697 includes the General Purpose Timer (GPT).

Five independent timers are included. Timer 0, 1, and 3 are interrupt-based timers, while timer 2 and

timer 4 are free-run timers.

Two modes are defined in interrupt-based timers:



One-shot mode—the timer stops when the timer counts down to 0.



Auto-repeat mode—the timer re-starts when the timer counts down to 0.

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