MT7697 datasheet(31/81 Pages) ETC2

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MT7697

Internet-of-Things Wireless Connectivity

Page 31 of 81

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Step 7: N9 executes from IDLM after PDA completes and CM4 executes from Cache/Flash or

TCM.

2.4.10.2 Watchdog Reset

Watchdog reset WDT_N9 is the watchdog timer for N9, and WDT_CM4 is the watchdog timer for

CM4.

When the WDT event of WDT_N9 occurs, WDT_N9 has the capability to



Reset N9 or issue an interrupt to N9.



Issue an interrupt to CM4 (can be masked by CM4 if it is not required to be received).

When the WDT event of WDT_CM4 occurs, WDT_CM4 has the capability to



Reset whole chip or reset CM4 only or issue an interrupt to CM4.



Issue an interrupt to N9 (can be masked by N9 if it’s not required to be received).

For both WDT_N9 and WDT_CM4, the WDT events can be triggered by time-out and software

programming.

For both WDT_N9 and WDT_CM4, the WDT has the capability to reset the other CPU or issue an

interrupt to the other CPU.

TOP_OFF (N9)

CM4_OFF

CIRQ

WDT_N9

NVIC

WDT_CM4

CM4_SW_RST_B

81080080[0]

N9_SW_RST_B

83080080[0]

PMU

D12: SYS_RST_N

PMU_RST_B

R16: AVDD45_BUCK

CM4_AON_XRESET_RST_B

POR_XRESET_RST_B

SEL: 8300917C[16]

CM4 MTCMOS

power CTRL

CM4_HW_RST_B

N9 RELEASE CM4

81020018[0]

RELEASE_CM4_RST_B

ARM CM4

WIC

CM4

peripherals

AON_XRESET_RST_B

RGU_HRESET_RST_B

N9 MTCMOS

power CTRL

N9_HW_RST_B

peripherals

CM4 to N9 interrupt: 83080080[31:30]

WDT_DUAL_CORE_SW_INTàCIRQ EINT 3

N9_TO_CM4_SW2 ingterrupt: 81080080[31:30]

WDT_DUAL_CORE_SW_INTàINT23

Note:

PMU_RST_B: power-on or over-current protection

CM4_WDT_RST_B: CM4 WDT reset

N9_WDT_RST_B: N9 WDT reset

CM4_AON_

HRESET_RST_B

CM4_RGU_HRESET_RST_B

WDT_N9 interrupt

N9_WDT_RST_BàINT13

81080030[3]

=1?

N9_WDT_RST_B

CIRQ INT10

CIRQ INT22

CIRQ EINT3

83080030[3]

=1?

INT10

INT13

INT23

Legend:

Reset:

Interrupt:

CM4_WDT_RST_B

Figure 2-9. WDT Structure

2.4.10.3 Reset Scenarios

The definitions of the cold reset and the warm reset are shown below:

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