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LTC3370 数据表(PDF) 6 Page - Linear Technology |
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LTC3370 数据表(HTML) 6 Page - Linear Technology |
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6 / 44 page  LTC3372 6 Rev. A For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VOUT = VINA-H = 3.3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Temperature Monitor VTEMP(ROOM) TEMP Voltage at 25°C 200 220 240 mV ∆VTEMP/°C VTEMP Slope 7 mV/°C OT Overtemperature Shutdown 170 °C OT Hyst Overtemperature Hysteresis 10 °C Low Voltage (LV) Buck Regulators VINA-H Input Operating Voltage l 2.25 5.5 V VOUT1-4 Regulated Output Voltage Set Point l 0.8 VINA-H V UVLO Undervoltage Lockout Threshold on VINA-H VINA-H Falling VINA-H Rising l l 1.95 2.05 2.05 2.15 2.15 2.25 V V IQ(VINA-H) Quiescent Current into VINA-H Pins, Per Enabled LV Regulator (Note 8) Burst Mode, FB1-4 = 0.82V Forced Continuous Mode, FB1-4 = 0V 25 400 35 550 µA µA ISD(VINA-H) Shutdown Current into VINA-H Pins 0 1 µA VFB1 Regulated Feedback Voltage for Regulator 1 l 792 800 808 mV VFB2-4 Regulated Feedback Voltage for Regulators 2-4 l 780 800 820 mV IFB1-4 Feedback Leakage Current FB1-4 = 0.85V –50 50 nA DMAX Maximum Duty Cycle FB1-4 = 0V l 100 % RPMOS PMOS On-Resistance ISW = 100mA, 1A – Per Power Stage 290 mΩ RNMOS NMOS On-Resistance ISW = –100mA, 1A – Per Power Stage 180 mΩ ILEAKP PMOS Leakage Current EN1-4 = GND –1 1 µA ILEAKN NMOS Leakage Current EN1-4 = GND –1 1 µA tSS Soft-Start Time (Note 10) 0.25 1.5 3 ms UV Rising Undervoltage RST Threshold Regulator 1 % Relative to Regulated VFB Hysteresis l –4 –2 1 –1 % % Rising RST Undervoltage Threshold Regulators 2-4 % Relative to Regulated VFB Hysteresis l –7 –5 1 –3 % % OV RST Overvoltage Threshold of Regulators 1-4 % Relative to Regulated VFB Hysteresis l +5 +7.5 –3 +10 % % ILIM PMOS Current Limit 1 Buck with 1 Power Stage (Note 9) 1.4 1.8 2.2 A 1 Buck with 2 Power Stages (Note 9) 3.6 A 1 Buck with 3 Power Stages (Note 9) 5.4 A 1 Buck with 4 Power Stages (Note 9) 7.2 A Interface Logic Pins (RST, WDO, WDI, CT, C1, C2, C3) IOH Output High Leakage Current RST, WDO 5.5V at Pin 1 µA VOL Output Low Voltage RST, WDO 3mA at Pin 0.1 0.4 V VIH WDI Input High Threshold l 1.2 V CT, C1, C2, C3 Input High Threshold l INTVCC – 0.4 V VIL WDI, C1, C2, C3 Input Low Threshold l 0.4 V tWDI(WIDTH) WDI Pulse Width l 80 ns |
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