LTC3370 datasheet(36/44 Pages) LINER

36 / 44 page

LTC3372

Rev. A

For more information www.analog.com

APPLICATIONS INFORMATION

The duty cycle percentage should be maintained

from cycle to cycle in a well-designed, low noise PCB

implementation.

3. Variation in the duty cycle at a subharmonic rate

can suggest noise pickup at the current or voltage

sensing inputs or inadequate loop compensation.

Overcompensation of the loop can be used to tame a

poor PCB layout if regulator bandwidth optimization

is not required.

4. Reduce VIN from its nominal level to verify operation

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering VIN

while monitoring the outputs to verify operation.

5. Investigate if any problems exist only at higher output

currents or only at higher input voltages. If problems

coincide with high input voltages and low output cur-

rents,lookforcapacitivecouplingbetweentheBOOST,

SW,TG,andpossiblyBGconnectionsandthesensitive

voltage and current pins.

If problems are encountered with high current output

loading at lower input voltages, look for inductive

coupling between CIN, bottom MOSFET, and the top

MOSFETcomponentstothesensitivecurrentandvolt-

age sensing traces. In addition, investigate common

groundpathvoltagepickupbetweenthesecomponents

and the exposed ground pad of the IC.

6. The capacitor placed across the current sensing pins

needs to be placed immediately adjacent to the pins

of the IC. This capacitor helps to minimize the effects

of differential noise injection due to high frequency

capacitive coupling.

7. If problems are encountered with high current output

loading at lower input voltages, look for inductive

coupling between CIN, Schottky and the top MOSFET

components to the sensitive current and voltage sens-

ing traces. In addition, investigate common ground

path voltage pickup between these components and

the exposed ground pad of the IC.

PCB Layout Considerations for LV Regulators

1. Each of the VINA-H input supply pins should have a

decoupling capacitor. The connections of the decou-

pling capacitors to their respective VINA-H pins should

be kept as short as possible. The GND side of these

capacitorsshouldconnectdirectlytothegroundplane

of the part. These capacitors provide the AC current

to the internal power MOSFETs and their drivers. It is

important to minimize inductance from these capaci-

tors to the VIN pins of the VINA-H pins.

2. The switching power traces connecting SWA-H to the

inductors should be minimized to reduce radiated EMI

and parasitic coupling. Due to the fast voltage swing

of the switching nodes, high input impedance sensi-

tive nodes, such as the feedback nodes, should be

shielded or kept far away from the switching nodes.

3. The return (GND side) of the switching regulators’

output capacitors should be connected to the exposed

pad (Pin 49, GND) of the IC through a ground plane.

Minimize the trace length from the output capacitors

to the inductor(s)/pin(s).

4. In a multiple power stage buck regulator application,

the trace length of switch nodes to the inductor must

be kept equal to ensure proper operation.

5. Kelvin connect the returns for RT, CT and the feedback

dividers to an isolated shape (ground copper “island”)

tied to the GND pad of the IC.

Other PCB Layout Considerations

CareshouldbetakentominimizecapacitanceontheTEMP

pin. If the TEMP voltage must drive more than ~30pF,

then the pin should be isolated with a resistor placed

close to the pin of a value between 10k and 100k. Keep

in mind that any load on the isolation resistor will create

a proportional error.

LTC3370 数据表(PDF) 36 Page - Linear Technology

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