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LTC3370 数据表(PDF) 21 Page - Linear Technology

部件名 LTC3370
功能描述  60V Low IQ Buck Controller Plus 4-Channel 8A Configurable Buck DC/DCs
PDF  44 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC3370 数据表(HTML) 21 Page - Linear Technology

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LTC3372
21
Rev. A
For more information www.analog.com
Table 1. Master Slave Program Combinations (Each Letter
Corresponds to a Low Voltage Power Stage)
PROGRAM
CODE
C3C2C1
BUCK 1
BUCK 2
BUCK 3
BUCK 4
000
AB
CD
EF
GH
001
ABC
D
EF
GH
010
ABC
D
E
FGH
011
ABCH
D
E
FG
100
ABC
DE
Not Used
FGH
101
ABCD
Not Used
EF
GH
110
ABCD
Not Used
E
FGH
111
ABCD
Not Used
Not Used
EFGH
Power Failure Reporting via RST Pin
Power failure conditions of all LV buck regulators are
reported by the single RST pin. Each LV regulator has an
internal power good signal. If LV Buck 1 output voltage
falls below 98%, or any of the Buck 2-4 outputs falls below
95%, of its programmed value, or if any LV regulator’s
output rises above 107.5% of its programmed value, its
internal power good signal is pulled low. If any internal
power good signal stays low for greater than 100μs, then
the RST pin is pulled low. The RST low signal indicates to
a microprocessor that a power failure fault has occurred.
The 100μs filter time prevents a false fault indication low
due to a output/load transient.
The internal power good comparators have hysteresis, so
the regulated output voltage of an enabled regulator has
to move back into the power good window by more than
the hysteresis for its power good signal to transition high.
Once all enabled LV regulator outputs are power good for
202ms (typical, CT = 10nF), the RST output goes high
impedance (pulled high by external resistor/current). If
all LV buck regulators are disabled, RST pulls low.
Temperature Monitoring and Overtemperature
Protection
To prevent thermal damage to the IC and its surrounding
components, the LV regulators have an overtemperature
(OT)function.Whenthe LTC3372dietemperaturereaches
170°C (typical) all LV buck switching regulators are shut
down and remain in shutdown until the die temperature
falls to 160°C (typical).
Thetemperaturemaybereadbackbytheuserbysampling
the TEMP pin analog voltage. The temperature, T, indicated
by the TEMP pin voltage is given by:
T =
VTEMP − 45mV
7mV
• 1°C
To reduce quiescent current (IQ), if all the LV buck regula-
tors are shut down, the temperature monitor also shuts
down and the TEMP pin becomes high impedance. The
temperature monitor can be disabled by tying the TEMP
pin to INTVCC to save IQ.
Programming the Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output voltage ripple.
The frequency of the internal oscillator (system clock)
is determined by an external resistor that is connected
between the RT pin and ground. The operating frequency
can be calculated using the following equation:
fOSC =
8 • 1011 • ΩHz
RT
The oscillator is designed to function with operating fre-
quencies between 1MHz and 3MHz, it has safety clamps
that prevent the oscillator from running faster than 4MHz
(typical) or slower than 250kHz (typical). Tying the RT pin
to INTVCC sets the oscillator to the default internal operat-
ing frequency of 2MHz (typical).
The internal oscillator can be synchronized through an
internal PLL circuit to an external frequency by applying
a square wave clock signal to the PLL/MODE pin. During
synchronization, the top MOSFET turn-on of LV buck regu-
lator 1 is phase-locked to the rising edge of the external
frequency source. All other LV regulators are locked to
the appropriate phase of the external frequency source.
OPERATION



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