LTC3370 datasheet(20/44 Pages) LINER

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LTC3372

Rev. A

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Burst Mode operation. However, continuous operation

has the advantage of lower output voltage ripple and less

interference to other circuitry. In forced continuous mode,

the output ripple is independent of load current. Clock-

ing the LTC3372 from an external source enables forced

continuous mode (see the Programming the Operating

Frequency section.)

When the PLL/MODE pin is connected for pulse-skipping

mode, the HV controller operates in PWM pulse-skipping

mode at light loads. In this mode, constant frequency

operation is maintained down to approximately 1% of

designed maximum output current. At very light loads,

the current comparator, ICMP, may remain tripped for

several cycles and force the external top MOSFET to stay

off for the same number of cycles (i.e., skipping pulses).

The inductor current is not allowed to reverse (discon-

tinuous operation). This mode, like forced continuous

operation, exhibits low output ripple as well as low noise

and reduced RF interference as compared to Burst Mode

operation. It provides higher low current efficiency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

LOW VOLTAGE REGULATORS

Low Voltage Buck Switching Regulator

The LTC3372 contains eight low voltage (LV) monolithic

1Asynchronousbuckswitchingpowerstages.Eachpower

stage contains an integrated PMOS top-side switch and

a NMOS bottom-side switch. The eight power stages are

controlled by up to four constant frequency peak current

mode controllers. All of the switching regulators are

internally compensated and need only external feedback

resistors to set their output voltages.

Each LV buck switching regulator can operate with an

independent input voltage and has its own FB and EN

pins to maximize flexibility. The enable pins have two

different enable thresholds that depend on the operating

state of the other LV regulators. When all of the LV regu-

lators are disabled, the EN pin threshold is 0.73V . Once

any LV regulator is enabled, the EN pin thresholds of the

remaining LV regulators are set to a precision internal-

reference-based 400mV. This precision EN threshold may

be used to provide event based sequencing via feedback

from other previously enabled regulators.

It typically takes 1ms for the internal bias circuits (in-

cluding INTVCC) to be ready after the first time RUN or

any EN pin rises above 0.73V. All regulators are disabled

during internal circuit start-up time. When a LV regulator

is enabled there is an additional 150μs delay before the

soft start ramp begins. All LV regulators have soft start

and forward and reverse current limiting to control inrush

currentduringstart-upandtoprovideshort-circuitprotec-

tion in normal operation.

The LV buck switching regulators are phased in 90° steps

toreducenoiseandinputripple.Thephasestepdetermines

the fixed edge of the switching sequence, which is when

the PMOS turns on. The PMOS off (NMOS on) phase is

subject to the duty cycle demanded by the regulator. Buck

1 is set to 0°, Buck 2 is set to 90°, Buck 3 is set to 270°,

and Buck 4 is set to 180°. In shutdown all SW nodes are

high impedance. The buck regulator enable pins may be

tied to VOUTvoltagesthrougharesistordivider,toprogram

power-up sequencing.

LV Buck Regulators with Combined Power Stages

Up to four adjacent LV buck regulators may be combined

inamaster-slaveconfigurationbysettingtheconfiguration

via the C1, C2, and C3 pins. These pins should either be

tiedtogroundorpinstrappedtoINTVCCinaccordancewith

the desired configuration code (Table 1). Any combined

SW pins must be tied together, as must any of the com-

bined VIN pins. EN1 and FB1 are utilized by Buck 1, EN2

and FB2 by Buck 2, EN3 and FB3 by Buck 3, and EN4 and

FB4 by Buck 4. If any buck is not used or is not available

in the desired configuration, then the associated FB and

EN pins must be tied to ground.

Any available combination of 2, 3, or 4 adjacent buck

regulators serves to provide up to either 2A, 3A, or 4A

of average output load current. For example, code 110

(C3C2C1) configures Buck 1 to operate as a 4A regulator

through VINA-H/SWA-H pairs A, B, C, and D, while Buck

2 is disabled, Buck 3 operates as a 1A regulator through

VINA-H/SWA-H pair E, and Buck 4 operates as a 3A regula-

tor through VINA-H/SWA-H pairs F, G, and H.

OPERATION

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