LTC3370 datasheet(22/44 Pages) LINER

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LTC3372

Rev. A

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OPERATION

The synchronization frequency range is 1MHz to 3MHz.

A synchronization signal on the PLL/MODE pin will force

all low voltage (LV) active buck switching regulators to

operate in forced continuous mode PWM.

The LV regulators switch directly off the internal oscillator

in 90-degree phase increments. The LTC3372 HV control-

ler switches at one-sixth (1/6) of the internal oscillator

frequency with a range of between 166kHz to 500kHz.

Windowed Watchdog Timer

A standard watchdog function is used to ensure that the

system is in a valid state by continuously monitoring the

microprocessor’sactivity.Themicroprocessormusttoggle

the logic state of the WDI pin periodically in order to clear

the watchdog timer. The WDI pin reset is read only on a

WDI falling edge, such that a single reset signal may be

asserted by pulsing the WDI pin for a time greater than

the minimum pulse width. If timeout occurs, a WDO low

is asserted for the reset timeout period, issuing a system

reset. Once the reset timeout completes, WDO is released

to go high and the watchdog timer starts again.

During power-up, the watchdog timer initiates in the

timeout state with WDO asserted low. As soon as the

reset timer times out, WDO goes high and the watchdog

timer is started.

A windowed watchdog function is implemented by add-

ing a lower boundary condition to the standard watchdog

function. If the WDI input receives a falling edge prior to

the watchdog lower boundary, the part considers this a

watchdog failure, and asserts WDO low (releasing again

aftertheresettimeoutperiodasdescribedabove).Thiswill

again be followed by another lower boundary time period.

The watchdog timer shuts down when RUN and EN1-4

are off (all HV and LV regulators are shut down). Tying the

CT pin to INTVCC disables the watchdog timer regardless

of the RUN and EN1-4 pins (HV and LV regulators either

on or off).

Choosing the CT Capacitor

The watchdog timeout period is adjustable and can be

optimized for software execution. The watchdog timeout

period is adjusted by connecting a capacitor between CT

and ground. Given a specified watchdog timeout period,

the capacitor is determined by:

CT = tWDO • 49.39 [nF/s]

For example, using a standard capacitor value of 10nF

gives a 202ms watchdog timeout period. Further, the other

watchdog timing periods scale with tWDO. The watchdog

lower boundary time (tWDL) scales as precisely 1/4 of

tWDO, the watchdog upper boundary time following the

previous WDI pulse scales as eight times that of tWDO, and

the watchdog upper boundary time following a watchdog

timeout scales as 64 times that of tWDO. Finally the RST

assertion delay will scale to the same time as tWDO.

These timing periods are illustrated in Figure 1. Each WDO

low period is equal to the time period t2-t1 (202ms for a

10nF CT capacitor, typical). If a WDI falling edge occurs

before the watchdog lower boundary, indicated by t3-t2

(50.6ms for a 10nF CT capacitor, typical), then another

watchdog timeout period occurs. If a WDI falling edge

occurs after the watchdog lower boundary (t4), then the

watchdog counter resets, beginning with another watch-

dog lower boundary period. In the case where a WDI low

transition is not detected by the specified time another

watchdog timeout period is initiated. This time is indicated

by t5-t4 (1.62s for a 10nF CT capacitor, typical). If a WDI

low transition is not detected within the specified time fol-

lowing a watchdog timeout period, then another watchdog

timeout period is initiated. This time is indicated by t7-t6

(12.9s for a 10nF CT capacitor, typical).

WDO

WDI

t1 t2 t3

t5 t6

3372 F01

Figure 1. WDO Timing Parameters

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