LTC3370 datasheet(35/44 Pages) LINER

35 / 44 page

LTC3372

Rev. A

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APPLICATIONS INFORMATION

Efficiency can be increased by combining more power

stages than are required to meet output current require-

ments. Conduction loss will decrease by adding power

stages. The overall efficiency will improve provided the

switching loss of the added power stage does not exceed

the reduction in conduction loss. For example, a buck

running at 900mA load may have a higher efficiency when

two power stages are combined to make a 2A buck. In this

example, the 900mA load is closer to the peak efficiency

power of the 2A buck this it is for a 1A buck. In addition

toefficiencyconcerns,combiningadditionalpowerstages

provides increased margin and transient capability. It is

therefore a good idea to explore combining any unused

power stages with active bucks in any given application.

Otherwise, any unused buck regulator should have it’s

FB and EN pins tied to ground. The VIN pin may be tied to

ground and the SW pin can float.

PRINTED CIRCUIT BOARD PCB LAYOUT

CONSIDERATIONS

PCB Layout Considerations for HV Regulator

1. The path formed by the top N-channel MOSFET, the

bottom N-channel MOSFET, and the CINTVCC capacitor

should have short leads and (PCB) trace lengths. The

output capacitor (–) terminals should be connected

as close as possible to the (–) terminals of the input

capacitor by placing the capacitor and kept away from

the loop described above.

For proper operation of the gate drivers, the BG and

TG traces should maintain low impedance. The length

of the BG and TG traces should be 1.0” or less and

the number of via should be kept minimum.

2. Kelvin connect the VOUT/EXTVCC pin directly to the (+)

terminal of COUT, or where the regulation needs to be.

The connection should not be along the high current

input feeds from the input capacitor(s).

3. Route the SENSE– and SENSE+ signals together with

minimum PCB trace spacing. The filter capacitor

between SENSE+ and SENSE– should be as close as

possible to the IC. Ensure accurate current sensing

with Kelvin connections at the current sense resistor.

Don’t connect the current sensing leads backwards!

The output voltage may still be maintained but the

current mode control will not be realized.

4. Place the INTVCC decoupling capacitor close to the

IC, between the INTVCC pin and power ground plane.

This capacitor carries the MOSFET drivers’ current

peaks. A ceramic capacitor placed immediately next

to the INTVCCpincanhelpimprovenoiseperformance

substantially.

5. Kelvin connect the return of the ITH network to an iso-

lated shape (ground copper “island”) tied to the GND

pad of the IC (refer to the ground copper “island(s)”

discussed in the Ground Planes section).

6. Keep the SW, TG, and BOOST nodes away from sensi-

tive control signals (ITH, SENSE+, SENSE–, RT, etc.).

These nodes have very large and fast moving signals

and therefore should be kept on the output side of the

HV regulator and occupy minimum PCB trace area.

Debugging HV Buck Controller on PCB

1. Probe and synchronize the oscilloscope to the switch-

ing nodes (SW, SWA-H pins). It is helpful to use an

oscilloscope current probe to monitor the currents in

the inductors.

2. Check for proper performance over the operating volt-

age and current range expected in the application. The

frequency of operation should be maintained over the

input voltage range down to near dropout and until the

peak of inductor current drops below the low current

operation threshold—typically 25% of the maximum

designed current level in Burst Mode operation.

In pulse-skipping mode, the frequency should main-

tain at even lower peak inductor current compared to

Burst Mode until a pulse is skipped to maintain the

regulation. The frequency in forced continuous mode

should not change with load current.

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