| 数据搜索系统,热门电子元器件搜索 |
|
GD25S512MDFJS 数据表(PDF) 32 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
|
|||||||||||||||||||||||||||||
GD25S512MDFJS 数据表(HTML) 32 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
32 / 87 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25S512MD 32 7.13. Quad Output Fast Read (QOFR 6BH or 4QOFR 6CH) The Quad Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure 22. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Figure 22 Quad Output Fast Read Sequence Diagram (ADS=0) Command 0 1 2 3 4 5 6 7 6BH CS# SCLK SI(IO0) SO(IO1) High-Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address 34 35 36 37 33 1 5 1 5 1 5 1 38 39 Byte1 32 42 43 44 45 41 46 47 40 5 Dummy Clocks 0 4 0 4 0 4 0 4 4 5 IO2 High-Z IO3 High-Z CS# SCLK SI(IO0) SO(IO1) IO2 IO3 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7 Byte2 Byte3 Byte4 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |