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GD25S512MDFJS 数据表(PDF) 71 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25S512MDFJS 数据表(HTML) 71 Page - GigaDevice Semiconductor (Beijing) Inc. |
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71 / 87 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25S512MD 71 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Figure 70 Power-on Timing Vcc(max) Vcc(min) VWI tVSL Chip Selection is not allowed Device is fully accessible Time Table 25 Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min Max Unit tVSL VCC (min) To CS# Low 2.5 ms VWI Write Inhibit Voltage 1.5 2.5 V 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each Byte contains FFH). The Status Register bits are set to 0, except QE bit (S9) and DRV0 bit (S21) are set to 1. 8.3. ABSOLUTE MAXIMUM RATINGS Table 26 Absolute Maximum Ratings Parameter Value Unit Ambient Operating Temperature -40 to 85 -40 to 105 -40 to 125 ℃ Storage Temperature -65 to 150 ℃ Applied Input/Output Voltage -0.6 to VCC+0.4 V Transient Input/Output Voltage (note: overshoot) -2.0 to VCC+2.0 V VCC -0.6 to 4.2 V |
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