DP83821 datasheet(39/86 Pages) NSC

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4.0 Register Set (Continued)

4.1.13 Power Management Control and Status Register

This register contains PM control and status information.

Reserved

Reserved (reads return 0)

PMEC

PME Clock

Returns 0 to indicate PCI clock not needed for PMEN.

18-16

PMV

Power Management

Version

This bit field indicates compliance to a specific PM specification rev level.

Currently set to 010b.

15-8

NLIPTR

Next List Item Pointer

Offset into PCI configuration space for the location of the next item in the

Capabilities Linked List. Returns 00h as no other capabilities are offered.

7-0

CAPID

Capability ID

Always returns 01h for Power Management ID.

Tag: PMCSR

Size: 32 bits

Hard Reset: 00000000h

Offset: 44h

Access: Read Write

Soft Reset: unchanged

bit

tag

description

usage

31-24

reserved (reads return 0)

23-16

BSE

Bridge Support Extensions

unused (reads return 0)

PMESTS

PME Status

Sticky bit which represents the state of the PME logic, regardless of the

state of the PMEEN bit.

14-9

DSCALE

Data Scale

reserved (reads return 0)

PMEEN

PME Enable

When set to 1, this bit enables the assertion of the PME function on the

PMEN pin. When 0, the PMEN pin is forced to be inactive. This value can

be loaded from the EEPROM.

7-2

Reserved

unused (reads return 0)

1-0

PSTATE

Power State

This 2 bit field is used both to determine the current power state of

DP83821, and to set a new power state.

00 - D0

01 - D1

10 - D2

11 - D3hot

DP83821 数据表(PDF) 39 Page - National Semiconductor (TI)

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